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Imperas and Industry Articles

Using SoC methodologies for RISC-V processor DV.

Semiconductor Engineering

 

As we celebrate over 50 years of microprocessors, the industry has embraced every generation of silicon process technology with architectural innovation plus new design methods that have supported innovations in almost every market segment. The interest around RISC-V is opening up increased activity around new approaches to optimize designs for the next generation of devices across multiple market segments…

 

To read the full…

Complexity is making this process more difficult, but new and better approaches are being developed.

Semiconductor Engineering

 

The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches.
Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact…

The role of engineers is changing, and they need to be picking up new skills if they are to remain valuable team players. There are several directions they could go in.

Semiconductor Engineering

 

Engineering has one constant — you innovate or fall by the wayside. That is true both for the things that are designed and for the engineers who design and build them. Today’s systems are putting new strains on engineers who can no longer be “tall and thin” or “short and fat.” Those descriptions pertain to an engineer who is either highly…

Continuous design innovation adds to verification complexity, and pushes more companies to actually do it.

Semiconductor Engineering

 

The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies.

The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature,…

Uses, challenges and tradeoffs in working with vector engines.

Semiconductor Engineering

 

A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that effort.
Vector instructions are a class of instructions that enable parallel processing of data sets. An entire array of integers or floating point numbers is processed in a single operation, eliminating the loop control…

The art of ISA design is the fine balance between gaining performance advantages and enhanced usability

Design & Reuse

The topic of RISC-V custom instructions is growing in importance. This article explains why this subject is becoming so significant, and outlines some of the previous approaches to processor hardware and software optimization to illustrate the techniques that are now possible with RISC-V.
RISC-V is an open ISA (Instruction Set…

Simulation is no longer up to the task of system-level verification, but making the switch to hardware-assisted verification can lead to some surprises if you do not fully plan ahead.

Semiconductor Engineering

 

Emulation is emerging as the tool of choice for complex and large designs, but companies that swap from simulation to emulation increasingly recognize this is not an easy transition. It requires money, time, and effort, and even then not everyone gets it right.
Still, there are significant benefits…

Building an open-source verification environment is not an easy or cheap task. It remains unclear who is willing to pay for it

Semiconductor Engineering

 

Defining an open-source verification methodology is a lot more difficult than just developing an open-source simulator. This is the reality facing open-source hardware such as RISC-V. Some people may be asking for the corresponding open-source verification, but that is a much tougher problem — and it is not going to be solved in the short term.
Part one…

OpenHW Processor DV Flow with Imperas RISC-V Golden Reference Model

 

The open specification of the RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition, implementations may be shared commercially or as open source, and adopters beyond the original design team can use these directly or as a basis for further modifications and enhancements.
The OpenHW Group is…