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Imperas and Industry Articles

No more not-invented here for the chip giant when it comes to processor architectures.

Engineering and Technology

Much like IBM after the PC architecture ran away from it and almost collapsed Big Blue’s highly profitable minicomputer and mainframe businesses, Intel has been through some soul-searching in the wake of Arm’s expansion from the world of cellular phones into just about everything else. 
Intel has moved from a company that sued relentlessly to try to maintain…

The functional verification task keeps growing. How well is the industry responding to growing and changing demands?

Semiconductor Engineering

 

Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW…

The September 8 learning event from Electronic Design will feature in-depth coverage of RISC-V architecture, hardware, software, and a robust panel discussion.

Electronic Design

 

The open [standard] RISC-V instruction set architecture (ISA) has taken the development community by storm as more companies have implemented chips based on RISC-V. The architecture is…

A fundamental shift in the economics of processing and new use cases are making ASICs cool again.

Semiconductor Engineering

 

Semiconductor Engineering sat down to discuss bespoke silicon and what’s driving that customization with Kam Kittrell, vice president of product management in the Digital & Signoff group at Cadence; Rupert Baines, chief marketing officer at Codasip; Kevin McDermott, vice president of marketing at Imperas…

New packaging technology is spawning new markets for IP, but it is not clear how many interface standards will be created and need to be supported.

Semiconductor Engineering

 

The design IP market has long been known for constant change and evolution, but the industry trend toward heterogenous integration and chiplets is creating some new challenges and opportunities. Companies wanting to stake out a claim in this area have to be nimble…

eeNews Europe

Imperas Software in the UK has extended the RVVI (RISC-V Verification Interface) with virtual peripherals to support asynchronous events and system level interrupts. RVVI is an open specification with a common methodology for the key components of the testbench to connect the RISC-V processor RTL instruction trace and reference models to fully support the lock-step-compare co-simulation.

The RVVI…

The latest posts on the EDA, IP and SoC Industries

 

EDACafe

 

The Design Automation Conference is back to its usual summer timeframe – again at the Moscone Center in San Francisco – with over one hundred exhibitors and a rich conference program that covers a wide range of topics including artificial intelligence, autonomous systems, RISC-V, security, embedded systems and more. Here we will briefly…

EENews Europe

It may come as a surprise that over 10 billion RISC-V processor cores have shipped. After all, it took ARM 17 years to reach that milestone in 2008, and RISC-V could be considered to be in its infancy with a consensus that the eco-system still needs to evolve, particularly around security. These two factors result from the open standard approach to an inherently custom technology. The instruction set can be easily extended to accelerate key instructions, reducing die area and…

EE Journal

 

I love computers (but only in a manly-man way, you understand). I’m not talking about the end-products that sit on our desks, hang out in our pockets, or lurk around us as we meander our way through the world, although I’m certainly fond of these little rascals—I’m much more interested in their “brains” in the form of their processing units where all the decision-making and number-crunching takes placel….
 

To read the full EE Journal article by…