Imperas Software Ltd. revised its ImperasDV for maintaining the expansion of RISC-V verification supporting both RTL bug detection and analysis while collaborating with design flow implementation in EDA SystemVerilog environments with Cadence, Siemens EDA, and Synopsys. Imperas leverages RISC-V for its ability to be customized for specific industry needs. “…
At this year’s RISC-V Summit, stakeholders rolled out solutions revolving around verification, security, and software-defined SoCs.
This week is the annual RISC-V Summit in San Jose, CA, where many of the major players in the industry get together to share technology and discuss the future of the RISC-V industry. Building off of the moment of the numerous RISC-V announcements in 2022, this…
Imperas Software announced the latest updates to ImperasDV to support the rapid growth in RISC-V verification as developers extend into established and emerging applications with new design innovations based on the flexibility of RISC-V. ImperasDV is the integrated solution for RISC-V processor verification that supports both RTL bug detection and analysis, when combined with design flow integration for the leading EDA…
RISC-V intellectual property company Andes Technology has certified simulation reference models from Imperas reference for use evaluating multi-core designs featuring the functional-safety-optimised Andes Core N25F-SE. At the same time, it also certified the complete range of Andes processor IP blocks with ‘Andes Custom Extension’ (ACE) support. Such virtual references run exactly the same binary code as any…
Realizing the benefits of digital twins is more complicated than translating data between tools.
Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale.
The glue between these various processes is data…
Prototypes are transforming rapidly to take on myriad tasks, but they are hampered by a lack of abstractions, standards, and interfaces.
Chipmakers are piling an increasing set of demands on virtual prototypes that go well beyond its original scope, forcing EDA companies to significantly rethink models, abstractions, interfaces, view orthogonality, and flows.
The virtual prototype has been around for at least 20 years, but…
How prepared the EDA community is to address upcoming challenges isn’t clear.
Dennard scaling is gone, Amdahl’s Law is reaching its limit, and Moore’s Law is becoming difficult and expensive to follow, particularly as power and performance benefits diminish. And while none of that has reduced opportunities for much faster, lower-power chips, it has significantly shifted the dynamics for their design and manufacturing.
Rather…
Does anyone really care if a design is bug-free? The cost probably would be prohibitive.
It is possible in theory to create a design with no bugs, but it’s impractical, unnecessary, and extremely difficult to prove for bugs you care about.
The problem is intractable because the potential state space is enormous for any practical design. The industry has devised ways to handle this complexity, but each has limitations, makes assumptions,…
From specific design team skills, to organizational and economic impacts, the move to bespoke silicon is shaking things up.
Bespoke silicon developers are shaking up relationships, priorities, and methodologies across the semiconductor industry, creating demand for skills that cross traditional boundaries, and driving new business models that leverage these enormous investments.
Bespoke silicon designers today are a rare breed, capable…