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Imperas and Industry Articles

The art of ISA design is the fine balance between gaining performance advantages and enhanced usability

Design & Reuse

The topic of RISC-V custom instructions is growing in importance. This article explains why this subject is becoming so significant, and outlines some of the previous approaches to processor hardware and software optimization to illustrate the techniques that are now possible with RISC-V.
RISC-V is an open ISA (Instruction Set…

Simulation is no longer up to the task of system-level verification, but making the switch to hardware-assisted verification can lead to some surprises if you do not fully plan ahead.

Semiconductor Engineering

 

Emulation is emerging as the tool of choice for complex and large designs, but companies that swap from simulation to emulation increasingly recognize this is not an easy transition. It requires money, time, and effort, and even then not everyone gets it right.
Still, there are significant benefits…

Building an open-source verification environment is not an easy or cheap task. It remains unclear who is willing to pay for it

Semiconductor Engineering

 

Defining an open-source verification methodology is a lot more difficult than just developing an open-source simulator. This is the reality facing open-source hardware such as RISC-V. Some people may be asking for the corresponding open-source verification, but that is a much tougher problem — and it is not going to be solved in the short term.
Part one…

OpenHW Processor DV Flow with Imperas RISC-V Golden Reference Model

 

The open specification of the RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition, implementations may be shared commercially or as open source, and adopters beyond the original design team can use these directly or as a basis for further modifications and enhancements.
The OpenHW Group is…

Sorting out what is meant by open-source verification is not easy, but it leaves the door open to new approaches

Semiconductor Engineering

 

Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification infrastructure, to providing open-source stream generators or reference models, to open-source simulators and formal verification engines.
Verification is about reducing risk …
 …

It has been an unusual DAC this year, as the show went virtual due to the Covid-19 pandemic. There was no exhibition floor as such, but there was a comprehensive programme of keynote speeches, presentations, tutorials and panel discussions

Electronics Weekly

There was a lot of activity around RISC-V, including a presentation by Imperas Software (www.imperas.com) entitled ‘What’s Next for RISC-V? Vectors, Verification, and Value-added Extensions’. During the…

The July 2020 edition of Mentor Graphics', a Siemens Business, Verification Horizons article and Verification Academy presentation on RISC-V Processor DV are now available online

Verification Horizons

 

As SoC developers adopt RISC-V and the design freedoms that an Open ISA (Instruction Set Architecture) offers, DV teams will need to address the new verification challenges of RISC-V based SoCs. The established SoC verifications…

RISC-V drives new attention to this market, but the cost/benefit equation is different for open-source hardware than software

Semiconductor Engineering

 

Open-source hardware continues to gain ground, spearheaded by RISC-V — despite the fact that this processor technology is neither free nor simple to use.

Nevertheless, the open-source hardware movement has established a solid foothold after multiple prior forays that yielded only limited success, even for processors. With demand for more customized hardware, and a growing…

Recently Embedded Magazine published a very interesting article with some insights on extending a RISC-V processor with custom instructions

Embedded

The open instruction set architecture (ISA) of RISC-V permits broad flexibility in implementation and offers optional features that can enable fresh approaches to resolving hardware-software design tradeoffs. Based on a modular structure, a number of standard extensions and options can be used to configure the base processor as a starting point.…