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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Improving Concurrent Chip Design, Manufacturing, And Test Flows

Realizing the benefits of digital twins is more complicated than translating data between tools.

Semiconductor Engineering

 

Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale.
The glue between these various processes is data, and the chip industry is working to weave together various steps throughout these flows by utilizing that data in more places. The goals include better visibility when making tradeoffs in heterogeneous designs, faster time to market, and improved reliability in the field. That will be enabled by in-chip and in-system monitoring capabilities, and bi-directional sharing and utilization of data back and forth across the design-through-manufacturing flow….
 

To read the full Semiconductor Engineering article by Ann Mutschler, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

RISC-V Custom Instruction Flow Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Vijay Krishnan, General Manager, RISC-V Ventures

    Intel

    The adoption of RISC-V is at an inflexion point across multiple markets and applications, and Intel fully appreciates that a healthy software ecosystem is critical for this new ISA to be successful.

    The availability of Imperas RISC-V reference models for the Professional Edition of Intel Pathfinder for RISC-V further strengthens the tools available to developers as new silicon designs move from concept to production.

  • Don Smith, Vice President Engineering

    MIPS, Inc.

    At MIPS we are experienced in bringing advanced computing technology, such as hardware multi-threading, to market as applications-class processors.

    As part of the strategic move to RISC-V, we fully appreciate the needs, implications and requirements for a high-quality verification solution. The Imperas Reference Model enables lock-step-compare with asynchronous events which is the foundation of our SystemVerilog testbench and verification methodology.