With the advent of RISC-V we have seen new design verification challenges emerge, and have been working with customers and open-source partners, as well as simulation vendors including Synopsys, since 2019 to develop RISC-V processor verification methodology. The outcome of this work is a co-simulation methodology where the device under test (DUT) and the reference model of the processor are run in lock-step, each executing the same program. The internal state of the two is continuously compared at the retirement of every instruction. Mismatches are reported immediately, enabling debug at the point of first failure. Another advantage to this methodology is that the reference model has the ability to respond to asynchronous events.
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