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Revolutionizing Embedded Software Development

Leadership Team

Simon Davidmann

Simon Davidmann

President & CEO
Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Simon was an executive or European GM with 5 US based EDA startups including Chronologic which pioneered the compiled code simulator VCS, and Ambit which was acquired by Cadence for $280M. Simon was one of the original developers of the HILO logic simulation system, and co-authored the definitive book on SystemVerilog.
Larry Lapides

Larry Lapides

Vice President Sales & Marketing
Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University's Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.
Peter Heller

Peter Heller

Chief Financial Officer
Peter Heller has twenty years of experience running the finance and administration of multi-national startup companies in the EDA industry. A Chartered Accountant, Peter was CFO of Co-Design Automation from inception to successful trade sale, and was responsible for the European finance of Novas, Ambit Design Systems, Chronologic and Gateway.
 

Comments

  • Chuanhua Chang, Chair of RISC-V International P Extension Task Group

    Andes Technology Corp.

    Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA.

    The RISC-V P extension defines a rich set of integer SIMD/DSP instructions operating on existing integer registers to support complex data processing within the constraints of real-time applications. However, the hardware specification is just the start - adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.

  • Allen Baum, Chair of the RISC-V International Architecture Test SIG

    Esperanto Technologies, Inc.

    Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture.

    The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.