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Revolutionizing Embedded Software Development

Leadership Team

Simon Davidmann

Simon Davidmann

President & CEO
Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Simon was an executive or European GM with 5 US based EDA startups including Chronologic which pioneered the compiled code simulator VCS, and Ambit which was acquired by Cadence for $280M. Simon was one of the original developers of the HILO logic simulation system, and co-authored the definitive book on SystemVerilog.
Larry Lapides

Larry Lapides

Vice President Sales
Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University's Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.
Kevin McDermott

Kevin McDermott

Vice President Marketing
Before joining Imperas, Kevin held a variety of senior business development, licensing, segment marketing, and product marketing roles at ARM, MIPS and Imagination Technologies focused on CPU IP and software tools. Previously Kevin was a principal analyst for IoT at ABI Research, focused on connected embedded and IoT, including value chains for IP, SoCs, software, standards and ecosystems. Kevin started his career in custom SoCs for mobile and embedded applications with semiconductor firms in both Europe and Silicon Valley. Kevin received his BSc degree in Microelectronics and Microprocessor Applications from the University of Newcastle upon Tyne, UK.
Peter Heller

Peter Heller

Chief Financial Officer
Peter Heller has twenty years of experience running the finance and administration of multi-national startup companies in the EDA industry. A Chartered Accountant, Peter was CFO of Co-Design Automation from inception to successful trade sale, and was responsible for the European finance of Novas, Ambit Design Systems, Chronologic and Gateway.
 

Comments

  • Philippe Luc, Verification Director

    Codasip

    Imperas are the pioneers in simulation technology and processor verification for RISC-V.

    While processor verification is not a new problem, there are many RISC-V suppliers, with customization and various levels of verification or conformance: customers are legitimately concerned about both quality and fragmentation. Codasip is very proud of our rigorous approach to verification– using Imperas as an important part of our quality process furthers extend our differentiation. The Imperas independence, reputation and technical strength provides our customers with further reassurance in our ‘best in class’ RISC-V processors.

  • Yunsup Lee, co-founder and CTO

    SiFive

    SiFive’s Core Designer allows our customers to customize our broad portfolio of RISC-V Core IP for their particular application. The donation of a robust, commercial-quality simulator such as riscvOVPsim™ will enable them to adopt RISC-V even faster. This is the level of close industry collaboration that will drive the successful adoption of RISC-V.