Chuanhua Chang, Chair of RISC-V International P Extension Task Group
Andes Technology Corp.
Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA.
The RISC-V P extension defines a rich set of integer SIMD/DSP instructions operating on existing integer registers to support complex data processing within the constraints of real-time applications. However, the hardware specification is just the start - adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.
Bill McSpadden, Principal VLSI Verification Engineer
Seagate Technology
The Imperas Golden RISC-V Reference Model helped us find many bugs in our cores.
However, the RISC-V architectural tests yielded no bugs, which is expected since the architectural tests are a subset of full verification.
