There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.
On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.
Publicly available Imperas documents:
To address the challenge of design verification for the Akaria products, NSITEXE turned to RISC-V solutions from Imperas Software and Cadence. The ImperasDV RISC-V processor verification solution, combined with the Xcelium RTL simulation and debug solution from Cadence, were instrumental in achieving first-time silicon success.
For more information, please email Imperas at info@imperas.com
With the advent of RISC-V we have seen new design verification challenges emerge, and have been working with customers and open-source partners, as well as simulation vendors including Synopsys, since 2019 to develop RISC-V processor verification methodology. The outcome of this work is a co-simulation methodology where the device under test (DUT) and the reference model of the processor are run in lock-step, each executing the same program. The internal state of the two is continuously compared at the retirement of every instruction. Mismatches are reported immediately, enabling debug at the point of first failure. Another advantage to this methodology is that the reference model has the ability to respond to asynchronous events.
A RISC-V processor has several defined decode spaces, for example custom0, custom1 etc. into which new custom instructions can be added. OVP Fast processor models can be extended without modification to the pre-compiled and verified base processor model source code using one or more extension libraries. An extension library can be loaded as part of a virtual platform definition in addition to the base processor model and can provide decode and implementation of behavior for the instructions as well as additional registers.
Including more timing information for the instruction execution provides a cycle approximate simulation. This provides a better approximation to the time of the execution of an application on the actual hardware. The additional timing information is loaded into the virtual platform as an extension library so there is no change to the functional behavior provided by the processor model.
This application goes through the complete flow of functional validation of the application, extension of the processor with custom instructions, analysis of the application execution and optimization of the custom instruction implementation and its documentation.
The ARM TrustZone technology adds a secure mode to the processor architecture and additional security signals to the AMBA bus, which are used by TrustZone-aware peripherals to prevent access to certain bus addresses when the processor (or other bus master) is not in secure mode.
As ARM TrustZone features are used for embedded systems, it becomes important to be able to comprehensively test the software that makes use of the TrustZone features. Key to comprehensive testing is the performance, controllability and visibility that virtual platforms provide.
This document focuses on best known methods for modeling TrustZone-aware peripherals in OVP platforms to achieve optimal performance.
Description of OVP Fast Processor Models and how to use them.
Also see the model variant specific documentation for very detailed information.