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Imperas in the News

Verification and debug of AI is a multi-level problem with several stakeholders, each with different tools and responsibilities.

Semiconductor Engineering

 

When an AI algorithm is deployed in the field and gives an unexpected result, it’s often not clear whether that result is correct.
So what happened? Was it wrong? And if so, what caused the error? These are often not simple questions to answer. Moreover, as with all verification problems, the only way to get to the root cause is to break the…

The C-Suite wants the chip industry to use PLM, but are their issues different enough that a more specialized black-box approach would be better?

Semiconductor Engineering

 

Product lifecycle management (PLM) and the semiconductor industry have always been separate, but pressure is growing to integrate them. Automotive, IIoT, medical, and other industries see that as the only way to manage many aspects of their business, and as it stands, semiconductors are a large black box in that…

Outlines vision for best-in-class RISC-V quality.

Codasip selects Imperas RISC-V Reference Models for RISC-V Processor Verification

Oxford, United Kingdom & Munich, Germany  – November 22nd, 2021 – Imperas Software Ltd., the leader in verification solutions for RISC-V, and Codasip, the leader in customizable RISC-V processor IP, today announced that Codasip has adopted Imperas reference designs and the Imperas DV solution for Codasip IP. Codasip has invested heavily into processor verification to…

4Q2021 release of Imperas simulator and reference models supports latest RISC-V Extensions for Bit Manipulation 1.0.0, Cryptographic (Scalar) 1.0.0, and Vector 1.0 plus Privilege Specification 1.12 as RISC-V Board formal approval is completed.

Imperas RISC-V Reference Models for latest ratified specifications

Oxford, UK – November 18th, 2021 – Imperas Software Ltd., the leader in RISC-V processor simulation and verification technology, today announced the latest product updates as a general…

Software and hardware interdependencies complicate debug in embedded designs. New approaches are maturing to help reduce debug time.

Semiconductor Engineering

 

Debugging embedded designs is becoming increasingly difficult as the number of observed and possible interactions between hardware and software continue to grow, and as more features are crammed into chips, packages, and systems. But there also appear to be some advances on this front, involving a mix of techniques, including hardware trace, scan chain-based debug,…

Technologies must evolve to keep up with changing demands, and emulation is no exception.

Semiconductor Engineering

 

Emulation is now the cornerstone of verification for advanced chip designs, but how emulation will evolve to meet future demands involving increasingly dense, complex, and heterogeneous architectures isn’t entirely clear.
EDA companies have been investing heavily in emulation, increasing capacity, boosting performance, and adding new capabilities. Now the big question is how else they…

Abstraction is the key to custom processor design and verification, but defining the right language and tool flow is a work in progress.

Semiconductor Engineering

 

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL)…

 

To read the full …

The cloud cements its role in embedded hardware design.

Engineering and Technology

In the summer of 2018, professors John Hennessy and David Patterson declared a glorious future for custom hardware. The pair had picked up the Association for Computing Machinery’s Turing Award for 2017 for their roles in the development of the reduced instruction set computer (RISC) architectural style in the 1980s. 
Towards the end of their acceptance speech, Patterson pointed to the availability of hardware in the cloud as…

Imperas simulation technology and reference models now available within the TESSY environment for the automation of embedded software testing and regression management

Imperas Models available for Razorcat TESSY tools

Oxford, UK – October 18th, 2021 – Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced Razorcat Developments, a leading provider of software testing tools for the embedded systems market, has integrated the Imperas fast processor reference models into the popular…