The open nature of the RISC-V means anyone can design a custom processor - moving the verification task from a few specialist suppliers to all SoC developers. This article looks at the industrial-grade verification and open methodology to support verification of an open-source CV32E40P core.
The amount of time, money and effort it takes to design a system-on-chip (SoC) means it is not surprising when engineering teams want to get it right first time. This long-held ideal doesn’t just happen on its own; it…
RCR Wireless News – “Well, technically...” Podcast featuring Katherine (Kat) Hsu from Imperas Software.
Imperas Software's Senior Account Manager Katherine (Kat) Hsu discusses the biggest trends in the semiconductor industry, why consumers should care about AI processors and the technical challenges that open standard RISC-V helps solve...
The full…
Mind-boggling number of options emerge, but which is best often isn’t clear.
The guideposts for designing chips are disappearing or becoming less relevant. While engineers today have many more options for customizing a design, they have little direction about what works best for specific applications or what the return on investment will be for those efforts.
For chip architects, this is proving to be an embarrassment of riches. However, that design freedom comes with huge…
The design freedoms of RISC-V offer developers flexibility for innovation – now processor IP verification quality is also a flexible option.
The RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address their target end application needs and requirements. RISC-V has a modular structure with many standard instruction extensions for…
Companies that invest in their employees’ education often get rewarded with more productive and happier workers.
Continuous education is essential for engineers, but many companies don’t recognize the value or they are unwilling to provide the necessary resources.
This should be a line of questioning before every new hire makes the decision about where they want to work, because it not only affects their future career, but also impacts the value they can provide…
Demand for faster processing with increasingly diverse applications is prompting very different compute models.
Data centers are undergoing a fundamental change, shifting from standard processing models to more data-centric approaches based upon customized hardware, less movement of data, and more pooling of resources.
Driven by a flood of web searches, Bitcoin mining, video streaming, data centers are in a race to provide the most efficient and fastest processing possible.…
Imperas simulation technology and reference model available for free, including test suites for basic processor hardware verification and compliance testing.
Oxford, UK – July 19th, 2021 – Imperas Software Ltd., the leader in RISC-V processor verification technology, announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension and architectural validation test suites.…
Imperas simulation technology and RISC-V reference models updated to cover the RISC-V P Extension for SoC architecture exploration and early software development.
Oxford, UK – July 12th, 2021 – Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V CPU cores and a Founding Premier member of the RISC-V International…
Time spent in debug is unpredictable. It consumes a large portion of the development cycle and can disrupt schedules, but good practices can minimize it.
Debug often has been labeled the curse of management and schedules. It is considered unpredictable and often can happen close to the end of the development cycle, or even after – leading to frantic attempts at work-arounds. And the problem is growing…
To read the full Semiconductor Engineering …