Using SoC methodologies for RISC-V processor DV.

As we celebrate over 50 years of microprocessors, the industry has embraced every generation of silicon process technology with architectural innovation plus new design methods that have supported innovations in almost every market segment. The interest around RISC-V is opening up increased activity around new approaches to optimize designs for the next generation of devices across multiple market segments…

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Complexity is making this process more difficult, but new and better approaches are being developed.

The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches.
Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact…

The role of engineers is changing, and they need to be picking up new skills if they are to remain valuable team players. There are several directions they could go in.

Engineering has one constant — you innovate or fall by the wayside. That is true both for the things that are designed and for the engineers who design and build them. Today’s systems are putting new strains on engineers who can no longer be “tall and thin” or “short and fat.” Those descriptions pertain to an engineer who is either highly…

Continuous design innovation adds to verification complexity, and pushes more companies to actually do it.

The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies.

The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature,…

Provides building blocks for RISC-V processor DV with free simulator, architectural validation test suites and SystemVerilog components for evolving Verification Ecosystem.

Oxford, UK – December 9th, 2020 – Imperas Software Ltd., the leader in RISC-V processor verification solutions, today announced significant enhancements to its RISC-V processor hardware design verification solutions. This release includes enhanced reference model with SystemVerilog…

RISC-V processor verification using SystemVerilog UVM test bench with step-and-compare between reference and RTL for dynamic testcase scenarios with coverage analysis.

Oxford, UK – December 8th, 2020 – Imperas Software Ltd., the leader in RISC-V processor verification technology, today confirmed the selection by Silicon Labs (NASDAQ: SLAB) of the Imperas RISC-V reference model as part of their RISC-V processor verification work. RISC-V…

riscvOVPsimPlus™ includes latest reference model and now offers expanded simulation features for debug & trace for early software development and hardware verification.

Oxford, UK – December 4th, 2020 – Imperas Software Ltd., the leader in RISC-V processor verification solutions, today announced that the Free riscvOVPsimPlus™ RISC-V reference model and simulator, which has been widely adopted across the RISC-V ecosystem, has been updated and extended…

Hsinchu, Taiwan and Oxford, UK – December 3rd, 2020 – Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V CPU cores and a Founding Premier member of the RISC-V International Association, and Imperas Software Ltd., a leader in high-performance software simulation and virtual platforms, announced today to extend their cooperation to the versatile Andes Custom Extension™ (ACE) and Imperas’ fast simulators. The joint…

Uses, challenges and tradeoffs in working with vector engines.

A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that effort.
Vector instructions are a class of instructions that enable parallel processing of data sets. An entire array of integers or floating point numbers is processed in a single operation, eliminating the loop control…