Imperas RISC-V Simulators
The Imperas ISS (Instruction Set Simulators), System Emulators, and Virtual Platforms have been developed and commercially supported for over 10 years. They are based on the Open Virtual Platforms (OVP) models and technology where there are currently over 200 processor model variants and over 250 platforms and peripheral models available.
The simulators are released to run in x86 Windows/Linux host PC environments.
For more information on the Imperas ISS using RISC-V visit: https://www.imperas.com/iss-imperas-instruction-set-simulator.
For information on RISC-V platforms and developing your own RISC-V models and simulations, visit: https://www.imperas.com/dev-virtual-platform-development-and-simulation.
If you need speed and require parallel simulation of your RISC-V designs, have a look at: https://www.imperas.com/quantumleap-virtual-platform-simulation-acceleration.
For debugging RISC-V designs, see below.
There is a good video to show the capabilities of the Imperas RISC-V products here: https://www.imperas.com/risc-v-bare-metal-demos-video-presentation. There are more videos on RISC-V at https://www.imperas.com/imperas-videos.
If you want to integrate a RISC-V simulation or development environment using simulation into a Continuous Integration environment such as Jenkins, have a look here: https://www.imperas.com/continuous-integration-using-jenkins-and-virtual-platforms.
Imperas FREE RISC-V Compliance Simulator
Imperas recently released a new ISS specifically for use in developing tests and compliance suites for RISC-V processors. It is free from GitHub - for more information please visit: https://www.imperas.com/riscvovpsim-free-imperas-risc-v-instruction-set-simulator.
Imperas simulators provide a gdbServer port enabling the connecting of RISC-V GBD debuggers to the simulator to allow the debugging of software running on bare metal platforms. This works well for a single processor design and Imperas comes with appropriate GDBs for the different cores and also provides the scripts and launch technology to allow very easy use of Imperas RISC-V simulators with GDB/Eclipse for IDE and single core debug.
If you are doing multi-processor design then a single GDB will not give you the debug experience that your project timescales will require... In that instance you should look at the Imperas Multi Processor Debugger - which allows the debugging of SMP and AMP, homeogeneous, and heterogeneous multi-core designs. The Imperas Multi Processor Debugger also enables co-debug of the source of the platform behavioral components.
For more information on Imperas RISC-V debug visit here: https://www.imperas.com/msdk-advanced-multicore-software-development-kit#Debug.
Imperas Verification, Analysis and Profiling tools
Imperas also provides many advanced tools to enhance the embedded software development methodology. For more information on these advanced tools visit here: https://www.imperas.com/msdk-advanced-multicore-software-development-kit.
Imperas models of standard RISC-V cores and platforms
Imperas and its partners develop many models of processors, cores and platforms. Several of these components can be used as is, and can added to your own platforms. Most of these models/platforms come as open source under an Apache 2.0 license and can be easily modified. If you need models of standard platforms, that you can use or extend - then you require Extendable Platform Kits (EPKs).
Many EPKs come out-of-the-box running with standard operating systems such as Linux or FreeRTOS.
For more informaton about models and platforms then please visit the OVP library pages to see currently availability for RISC-V: https://www.ovpworld.org/library/wikka.php?wakka=RiscVpage.
Videos showing RISC-V simulation and debug
There are several video on the use of RISC-V ISA and core models with the Imperas simulation and debug solutions.
Please have a look at: https://www.imperas.com/imperas-videos where you will find videos showing very fast simulation on bare metal, operating systems running like FreeRTOS, and multi-core debug across RISC-V based platforms.
As we roll out our different processor models and platforms we will provide more videos. When we completed our RV64GC model and added an Extendable Platform Kit (EPK) which includes a UART, CLINT, PLIC and processor that can boot the standard Linux kernel with the busybear-linux filesystem image we created the video: https://www.imperas.com/risc-v-rv64gc-virtio-linux-epk-booting-linux-kernel-busybear-linux-file-system.
We then modeled the HiFive Unleashed development board from SiFive. This includes the U54-MC 5 core 64bit RISC-V processor that can run SMP Linux. To see this virtual platform booting SMP Linux and being debugged with the Imperas Multi-Core Debugger look at the video here.
Video showing flow and methodology for adding RISC-V custom instructions including debug, profiling, and coverage
To see advanced usage of the Imperas tool suites for extending RISC-V processors with custom instructions, view this video: https://www.imperas.com/risc-v-custom-instruction-design-and-verification-flow.