For a demo of how easy it is to download the OVP simulator and models, and a quick walk through downloading and running the applications running on a RISC-V Fast Processor Model, please watch this video.
Steve Richmond, Co-chair of the OpenHW Group Verification Task Group
Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.
The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.
Shuzo Tanaka, Vice President
Virtual platforms are moving into the mainstream of embedded software flows. Imperas tools and models lead the market, and adding distribution to our relationship enables us to provide complete and comprehensive solutions to our customers.