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Revolutionizing Embedded Software Development

RISC-V Bare Metal Demos Video Presentation

For a demo of how easy it is to download the OVP simulator and models, and a quick walk through downloading and running the applications running on a RISC-V Fast Processor Model, please watch this video.

Comments

  • Gerard Rauwerda, CTO

    Recore Systems

    Imperas allowed us to quickly add our own components and build the topologies which we wanted to test. We had our first demo up and running in 20 minutes, and it took us just a few days to build a reference hardware architecture based on components in the Extendable Platform Kit (EPK). Last but not least, after just a few months we could start playing with our own many-core operating system on our many-core hardware design. The ease of use of the EPK, together with excellent Imperas documentation and support, have kick-started our FlexaWare platform development.

  • Alexander Redkin, CEO

    Syntacore

    As one of the first IP providers for RISC-V cores, we see the importance of compliance as the RISC-V ecosystem develops. riscvOVPsim is a solid starting point for developers looking for a RISC V ISS (Instruction Set Simulator) for test and verification.