Imperas is launching some very interesting approaches to processor modeling and software testing.  Historically processor models have been used in relatively small numbers, despite their enormous benefits. The Imperas business model has the potential to make processor modeling an affordable approach used widely across the industry.

RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations.

The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.