Imperas technology and solutions for RISC-V Verification including Verification IP, Processor Reference Models, Virtual Prototypes, and Software Development Tools
Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced their participation at RISC-V Days Tokyo 2022 Autumn in Tokyo, Japan. Imperas, together with local partner eSol Trinity, will provide insights and solutions for RISC-V processor verification and extensions with custom instructions, in conjunctions with tools and solutions to accelerate embedded software development.
Platinum talk: 'RISC-V high quality verification with open standard RVVI and ImperasDV'
Abstract: RISC-V is extending the design freedoms for SoC developers with optimized processors. This talk outlines RVVI (RISC-V Verification Interface), an open standard interface for RISC-V processor verification with efficiency, reusability and flexibility. Highlights will cover examples of testing some popular open-source IP cores, and guidance for new processor DV projects.
• Speaker: Shuzo Tanaka – eSOL TRINITY Co., Ltd.
• Co-Author: Simon Davidmann – Imperas Software
• Co-Author: Lee Moore – Imperas Software
• When: TBD
Exhibit: Stop by the Imperas booth and see all the latest demonstrations and virtual platform technology for RISC-V based designs, including verification and custom instruction, plus support for the latest RISC-V specifications for Vectors and Bit Manipulation. For more information, or to set up meetings with Imperas, please contact email@example.com.
About RISC-V Days Tokyo 2022 Autumn
When: November 16 to 18, 2022.
Where: Pacifico Yokohama, Tokyo, Japan.
For more information and registration please visit RISC-V Days Tokyo 2022
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.
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