Silicon Labs selected Imperas simulation tools and RISC-V models for our design verification (DV) flow because of the quality of the models and the ease of use of the Imperas environment.
The Imperas golden reference model of the RISC-V core and their experience with processor RTL DV flows were also critical to our decision.
Kiran Vittal, senior director of Partner Alliances Marketing
Synopsys, Inc.
RISC-V adoption is growing across key market segments as SoC teams explore the flexibility of an open standard ISA for optimized processors.
Our collaboration with Imperas, leveraging Synopsys’ leading simulation and debug solutions, enables our mutual customers to address verification complexities for RISC-V processor cores and quickly achieve coverage convergence.