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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Sweeping Changes Ahead For Systems Design

Demand for faster processing with increasingly diverse applications is prompting very different compute models.

Semiconductor Engineering

 

Data centers are undergoing a fundamental change, shifting from standard processing models to more data-centric approaches based upon customized hardware, less movement of data, and more pooling of resources.
Driven by a flood of web searches, Bitcoin mining, video streaming, data centers are in a race to provide the most efficient and fastest processing possible. But because there are so many different types of data, disparities in lifetimes among components, and so much change in software, the magnitude, speed, and breadth of these changes is unprecedented….
 

To read the full Semiconductor Engineering article by Ann Steffora Mutschler, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Frankwell Jyh-Ming Lin, President

    Andes Technology

    To support the ever-increasing features of the emerging applications, SoC engineers face the challenges of the design complexity and time-to-market. They need powerful development tools such as fast system simulation for architectural exploration and SW development, emulation for functional verification and system validation, performance optimization, tough bugs tracing and embedded analytics. That is why Andes has worked with some of the partners on V3 AndesCore processors for many years. We are now collaborating with Imperas, Lauterbach, Mentor, and UltraSoC to provide those advanced development tools for our new V5 AndesCore N25 and NX25, and the RISC-V community.

  • Michael Wittner, Managing Director

    Razorcat Development GmbH

    Over the past 20 years TESSY has become the established reference platform for automatic regression testing and software maintenance.

    In supporting the Imperas reference models and virtual platforms, our customers benefit from the quality reference models and flexibility to cover the configurations supported in deployed devices and plan for the next generation of hardware enhancements.