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The RISC-V Verification Interface (RVVI) – test infrastructure and methodology guidelines

The DVCon 2023 edition of Siemens EDA Verification Horizons.

Verification Horizons


The open standard ISA (Instruction Set Architecture) of RISC-V is at the forefront of a new wave of design innovation. The flexibility to configure and optimize a processor for the unique target application requirements has a lot of appeal in emerging and established markets alike. RISC-V can address the full range of compute requirements such as an entry-level microcontroller, a support processor (for such functions as power management, security etc.), right up to the state-of-the-art processor arrays with vector extensions for advanced AI (Artificial Intelligence) applications and HPC (High-Performance Computing).

This wave of innovation is generating a tsunami in verification as more and more SoC development teams face the complexities of RISC-V processor verification. Processor verification is not new, but in the past most processor IP was single-sourced, and the basic assumption of the SoC verification plan was based on high-quality pre-verified IP cores.

RISC-V represents the greatest migration in verification responsibility in the history of EDA, which in turn is driving the formation of a new RISC-V verification ecosystem. With the open standard ISA of RISC-V, every SoC team that explores the design freedom of RISC‑V will also need to undertake some level of Design Verification (DV). Since the desired quality level and completeness is yet another freedom offered by RISC-V, developers have new DV options to explore as well. Fortunately, RISC-V processor verification methodology is maturing, and new standards such as the RISC-V Verification Interface (RVVI) will help these teams gain a head start on their core verification project…


To read the full Verification Horizons article, click here.