Imperas presents together with Dolphin Design the latest advances for RISC-V Verification with RISC-V Processor Reference Models and Verification IP
Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced their participation at DVCon Europe 2022 with a paper and presentation on RISC-V verification co-authored with Dolphin Design.
Development and Verification of RISC-V Based DSP Subsystem IP: Case Study
• Co-author: Pascal Gouedo – Dolphin Design
• Co-author: Damien Le Bars – Dolphin Design
• Co-author: Olivier Montfort – Dolphin Design
• Co-author: Lee Moore – Imperas Software
• Co-author: Aimee Sutton – Imperas Software
• Co-author: Larry Lapides – Imperas Software
• When: Wednesday Dec 7, 1:15pm – Forum P3.2
The RISC-V ISA has been gaining momentum in the semiconductor community because of the design freedoms of the open specification. To date, the focus in the community has been on the development and verification of individual domain-specific processors and the software that runs on them. One of the use cases for those domain-specific processors is the instancing of multiple processors to create processing subsystems for AI/ML, audio processing and general-purpose digital signal processing. This subsystem level of processor integration poses new challenges for both hardware and software, not only with the individual RISC-V processors but also at the subsystem level.
New challenges faced include the verification of custom features in the processors, development of the communication fabric for the multiple processors and software development on the processor subsystem. There are also some existing challenges, specifically the verification of the base RISC-V processor.
To accelerate the development of software, a virtual platform (software simulation) flow is used. This starts with just a single processor model, the same OVP model used for DV, instantiated in a SystemC environment for basic bare metal software bring up.
This paper will present the single processor DV and virtual platform methodologies and results, and discuss the extensions to these methodologies for DV and software development for the processing subsystem.
Panel: Are processor/SoC discontinuities turning verification on its head?
• Moderator: Mike Bartley, Tessolve (formerly CEO of TVS)
• Panelists: Bodo Hoppe, Distinguished Engineer Verification, IBM
• Panelists: Rupert Baines, CMO, Codasip
• Panelists: David Kelf, CEO, Breker Verification Systems
• Panelists: Duncan Graham, Applications Engineering, Imperas
• When: Wednesday Dec 7, 4:45pm – Main Ballroom
A symbiotic relationship exists between modern System-on-Chip (SoC) requirements and processor technology evolution. As SoCs are applied to a broader range of applications with specialized needs, for example safety and security in the case of automotive and medical electronics, processor suppliers must adapt their devices accordingly while ensuring that performance and power objectives continue to be met.
To meet these needs, processor clusters leverage specialized instructions and accelerators across coherent fabrics driven by performance optimized software. This has recently been augmented by the advent of open instruction set architectures and the inclusion of custom instructions. The impact of this evolution is most felt during the verification process. Ensuring instruction set compatibility and efficient load-store operation in processor that must meet ever more stringent SoC requirements has verification teams scrambling. Are we at a verification inflexion point where the whole process requires revamping?
Mike Bartley, a well-known verification technologist and commentator, will moderate this panel made up of verification experts on the frontline of SoC challenges. They will explore evolving SoC requirements, the impact of new processor developments and their own experience at meeting corresponding verification needs. Expert panelists from a leading processor provider and SoC integrator will compare their findings with two noted EDA SoC/processor verification company leaders. Attendees will learn what is coming in terms of SoC developments and strategies for dealing with these. Audience participation will be encouraged.
About DVCon Europe 2022
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