Imperas is now a part of Synopsys
Imperas contribution includes updates on the latest advances for RISC-V Verification and ecosystem support for RISC-V adoption.
Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced their participation at HiPEAC23 in Toulouse, France. The HiPEAC (European Network on High-performance Embedded Architecture and Compilation) conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for general-purpose, embedded and cyber-physical systems. Imperas will present a talk on the RISC-V verification ecosystem and also participate on a panel discussion for RISC-V adoption in HPC.
Conference talk: ‘New open verification standards for the RISC-V verification ecosystem’
Abstract
As an open standard ISA, RISC-V has attracted attention across the semiconductor ecosystem based on new freedoms of design optimizations. With this surge in design innovation the challenge for verification grows from SoC integration to include complete CPU DV too.
This talk will highlight the key aspect of a RISC-V verification plan based on work at OpenHW to deliver quality open-source IP cores with industrial strength verification for adoption in standard commercial tools flows. The new open standard of RVVI (RISC-V Verification Interface) supports the full flexibility of RISC-V for designs with privilege modes, vectors, out-of-order pipelines, multi-threading, multi-hart, plus user defined custom instructions and extensions. In conjunction with a high-quality reference model this interface allows straightforward DV and can lead to successful CPU verification.
Speaker: Jon Taylor – Imperas Software
When: Monday Jan 16 2023: 2:00pm CEST
Panel session: ‘European RISC-V in HPC prospective’
Chair: (TBC)
Panelist:
• Jon Taylor - Imperas
• Roger Espasa - SemiDynamics
• Zdenek Prikryl - Codasip
• Michael Chapman - Cortus
When: Monday Jan 16 2023: 4:45pm CEST
About the HiPEAC23 Conference
When: January 16-18, 2023.
Where: Pierre Baudis Convention Centre, Toulouse, France.
Web link: https://www.hipeac.net/2023/toulouse/#/
About Imperas
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.
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Comments
Charlie Hong-Men Su, CTO and Senior Vice President
Andes Technology CorpIn commercial semiconductor IP, quality is perhaps the highest priority for successful customer engagements, the extensive test and verification process is best achieved with extensive simulator-based testing. We have already certified the Imperas RISC-V model and simulation technology for Andes N25 and NX25 processors so expect that riscvOVPsim will quickly be adopted as an industry standard reference simulator.
Rick O’Connor, Founder and CEO
OpenHW GroupThe OpenHW Group charter is to deliver high quality processor IP cores for our leading commercial members and open source community adoption.
Central to this goal, the OpenHW Verification Task Group developed and published a DV test plan and implemented an open engineering-in-progress approach as we complete the verification tasks using the Imperas golden RISC-V reference model.