Imperas presents the latest advances for RISC-V Verification with RISC-V Processor Reference Models and Verification IP.
Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced their participation at Verification Futures UK 2023, including a talk on the latest developments and implication for RISC-V processor verification.
RISC-V verification and implications of the 5:1 ratio of DV to design engineers
Simon Davidmann, President & CEO at Imperas Software
It has been reported that a typical SoC project plan assumes 1 DV (Design Verification) engineer to every design engineer as a basic 1:1 ratio. But for processor verification, the ratio of DV engineers is closer to 5:1. The rapid growth in the adoption of RISC-V and the design freedoms offered by the open standard ISA (Instruction Set Architecture) specification is driving a new wave of processor developers pushing the boundaries of optimized processors. As the industry prepares for the coming tsunami of verification work this talk highlights the growing RISC-V Verification Ecosystem based on open standards and extensions to the classic SoC methods of SystemVerilog and UVM.
RISC-V represents the greatest shift in verification responsibility as the challenge of processor verification shifts to all developers exploring the new design freedoms of RISC-V.
Thursday, June 22, 2:20pm
About Verification Futures UK 2023
When: June 22, 2023
Where: FREE to attend in-person Reading (UK) or online
Web link: https://www.tessolve.com/verification-futures/vf2023-uk
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.
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