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RISC-V International: Developing standards-based verification environments for extensible RISC-V processor cores

The open ISA of RISC-V means any SoC developer can now design a custom processor - moving the verification task from a few specialist suppliers to all SoC developers. This article looks at the industrial-grade verification and open methodology as used by the OpenHW verification working group.

RISC-V Processor Design Verification (DV)

One of the appealing things about open-source is that it invites modification to the underlying technology. In the case of the RISC-V instruction set architecture (ISA), this includes adding user-defined extensions to the processor core itself. Naturally, this level of extensibility has implications on the design flow, particularly if the core is going to be instantiated in silicon within an SoC or ASIC device…

To read the full article published by RISC-V International, click here.