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Imperas Expands Partnership with Valtrix to Address Growing RISC-V Verification Market

Imperas simulation technology and RISC-V reference models now available pre-integrated within Valtrix STING for advanced RISC-V Processor Verification.

Imperas and Valtrix expand partnership for RISC-V Verification

Oxford, UK – June 30th, 2021 – Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced a multi-year distribution and support agreement with Valtrix Systems, provider of design verification products for building functionally correct CPU and system-on-chip implementations, to address the rapidly expanding worldwide market for RISC-V processor verification. RISC-V verification has 3 main components: 1) a design to test, 2) a reference model for comparison, and 3) tests to fully exercise the design. A verification plan details the objectives in terms of coverage metrics and requirements including asynchronous events, debug modes, and the analysis-to-resolution process.

A key advantage of the Valtrix STING verification environment and test generator is the ease of use, including user controls for every test parameter, enabling every test condition to be mapped to a particular test configuration for the Device Under Test (DUT). Since a processor is by definition a complex state machine with multi-modes, dynamic testing has proven to be the most trusted option for targeted test suites and the interactions with asynchronous events. The key task for DV teams is to analyze bugs and then adapt the test case scenarios to fully explore the related state-space for additional issues.

The adoption of RISC-V by SoC developers is being driven in part by the flexibility that allows domain-specific features that can be fine-tuned to address the key application requirements. This adoption momentum on the design side is now driving SoC teams to adapt their verification and test plans to also cover the full processor DV tasks. This is causing a dramatic shift in the specialist processor verification tasks from a few mainstream IP providers to all SoC teams. This growth is also driving the efficiency goals to improve the DV analysis and resolution process to align the processor core schedule with the schedules of the target SoC design. On average the verification of a processor core is an order of magnitude more complex than the rest of the SoC that surrounds it. This momentum is driving the requirement for more efficient RISC-V verification solutions worldwide. 

“The flexibility of RISC-V helps us address domain-specific requirements with custom processors that go beyond the roadmap of the mainstream IP providers,” said Richard Bohn, Engineering Director at Seagate Technology, the world’s leading manufacturer of hard drives. “Designing a high-performance RISC-V processor that achieved up to 3x the performance in critical workloads was no small feat. We needed to balance the features and options with the verification implications. The combined solution of Imperas golden reference models and Valtrix STING has helped us to achieve our verification and schedule goals.”


“Ideally any test should provide a clear pass or fail indication. In the case of RISC-V processor DV this is achieved with a comparison against a quality reference model,” said Shubhodeep Roy Choudhury, Managing Director & Co-founder, Valtrix. “STING helps generate portable, architecturally correct and self-checking tests targeted at the corner-case scenarios by automating the comparison of the DUT against the Imperas reference model results.”


“As SoC verification teams adapt to the complexities of DV for a RISC-V processor, we see a growing demand for efficiency as teams scale resources over multiple overlapping projects, continuous integration, and regression testing,” said Simon Davidmann, CEO at Imperas Software Ltd. “Having successfully worked with Valtrix in supporting many mutual customers projects, this partnership now offers a frictionless path for STING users to our simulation technology and RISC-V reference models.”


Valtrix STING is available now with the pre-integrated Imperas RISC-V reference model. The combined solution covers the full RISC-V specification for user, privilege, and debug modes, including all ratified standard extensions, and the near ratified (stable) specifications for Bit Manipulation, Crypto (Scala), DSP, Hypervisor, and Vectors. STING plus Imperas is also upgradable to add support for custom instructions and extensions.

Lead customers are already engaged with designs featuring multithreading, multi-hart, and other complex microarchitectural features.


About Valtrix's STING Design Verification Tool
STING, the flagship product of Valtrix, is a design verification platform for RISC-V based implementations. It can be configured to generate portable bare-metal programs containing self-checking architecturally-correct test stimulus, which can then be enabled on simulation, FPGA prototypes, emulation, or silicon. STING also provides a RISC-V architecture verification suite to provide users an easy ramp into verification readiness.


About Imperas

Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at and the Open Virtual Platforms (OVP) website at

For more information about Imperas, please see Follow Imperas on LinkedIntwitter @ImperasSoftware and YouTube.

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