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Adding Value To Open-Source RISC-V Cores With Verification

A collaboration to verify the Open Source CV32E40P (PULP RI5CY) core using industrial grade techniques provides a set of guidelines for the community.

The Lost Art of Processor Verification


Modern SoC verification has matured to the point that some are suggesting the use of the word ‘prototype’ when referring to the first silicon samples is now unnecessary. This is due in part to the commercial EDA industry, which has provided the innovation and tools used throughout the design process, and the verification work that has become a specialty in its own right with dedicated conferences and standards.

The open-source ISA of RISC-V has generated a lot of interest around custom processor design options and the associated design freedoms beyond the roadmap of the mainstream processor IP providers. Thus, RISC V has enabled any SoC developer to consider designing a bespoke processor, which in turn has stimulated the interest in adapting the established SoC design verification (DV) flows based on UVM and SystemVerilog to also address the complexities of processor verification. On top of this, the open-source ISA of RISC-V has renewed the interest in open-source hardware IP. With this background, the OpenHW Group was formed to enable the community to collaboratively develop open-source hardware IP with industrial strength verification, to provide the trust and confidence that is normally associated with commercial IP quality…

To read the full blog post by Steve Richmond (Silicon Labs), Mike Thompson (OpenHW Group), and Lee Moore (Imperas Software) on Semiconductor Engineering, click here.