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DEV - Virtual Platform Development and Simulation


Controller, Standard and Multicore Virtual Platform Developer Products


The Imperas Developer products consist of tools, models and infrastructure components critical for the high quality, rapid development and verification of embedded software, utilizing virtual platforms. The Developer products provide the necessary capabilities to develop platforms, including software simulation capability to execute embedded code on the platforms.

Developer Product Flow

To enable the rapid creation of accurate and efficient virtual platforms, the Developer products contain:

  • Imperas Model Library, a comprehensive range of processor, platform and peripheral models
  • iGen Model Generator, which automates the creation of a code framework for new models, simplifying the laborious and error prone initial phase of model generation. These models are built around the platform development infrastructure of Open Virtual (OVP), an open industry standard noted for enabling the efficient modeling of virtual platforms that leverages industry standards
  • Targeted simulation solution for the execution of embedded code, dependent on the processor capability required. The simulator can operate with GDB and the Eclipse IDE, as well as the Imperas Multicore Software Design Kit.

Developer Products

The products are divided into three product groups based on processor type and capabilities, as follows:

  • The Controller Developer (C*DEV) contains capability for the development of code for single processor or single core multi-processor systems, primarily controllers.
  • The Standard Developer (S*DEV) targets homogeneous systems, which may include several single or multi-processor cores of the same type.
  • The Multicore Developer (M*DEV) includes a complete range of functionality for systems using single or multi-processor cores in homogeneous or heterogeneous configurations.


Imperas has pioneered three technological advancements, which revolve around the simulation engine and its interaction with models and environment components to significantly improve the user experience, as follows:

  • Unique, powerful capabilities targeting improved engineering efficiency, allowing hard to identify problems to be rapidly identified and rectified.
  • High software execution performance enabling the largest code base to be run far faster than previously possible in a simulation based software development environment.
  • Significant ease-of-use characteristics, driving an intuitive, recognizable user interface and reducing the environment learning curve.
Using virtual platforms allows early start to software development


The Imperas Model Library

Imperas has developed an extensive model library of processors, peripherals and reference platforms for use in Virtual Platforms.

The model library contains more than 160 models of CPU devices from most of the major embedded processor vendors. Included in this extensive range are the complete families of the ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8 architecture-based processors, including models of the ARM Cortex-M, Cortex-R and Cortex-A series of devices. The entire collection of the Imagination MIPS 32 and 64 bit processor models is also contained in the library. Processors such as the PowerPC, OpenCores OR1K, the Renesas v850 processor range, Altera Nios II, Xilinx Microblaze, and the Synopsys ARC range are all modeled at the Instruction Accurate (IA) level. There are also models of the open source RISC-V RV32 and RV64 processors. All processor functionality is faithfully reproduced, including noted hard-to-model capabilities, such as ARM’s TrustZone and virtualization features.

Almost one hundred common peripheral models may also be downloaded from the library.

In addition to the processor and peripheral models, many reference platforms are also included. These represent well-known industry examples, such as the MIPS Malta, ARM Integrator and Versatile Express, Renesas V850/PHO3, Xilinx ML505, Atmel AT91SAM7, Altera CycloneV platforms.

Imperas Image Library

The models are written in C and use the OVP APIs, enabling execution on OVP compliant simulators such as the Imperas simulator. Additionally, all the models have the Imperas development environment tightly integrated within. Many of the models are available as open source and all may be downloaded directly from the website.

One reason for the extensive range of processors and other models included in the library is ease of modeling provided by the OVP APIs. APIs are available for modeling platforms, processors, behavioral models and peripherals, each optimized for the particular modeling style required. The modeling standards allow for functionality to be included quickly while maintaining model performance and ease of use, reducing a typical multi-month development project down to just a few weeks.

All models may be incorporated within a SystemC environment. The models are delivered with a bus transactional interface and this has been leveraged to provide a high speed TLM 2.0 interface layer that allows their use in a SystemC TLM 2.0 environment, enabling the fastest possible simulation performance. 

All models are available directly from the link.

iGen Model Framework Generator

To aid with model creation, all the Imperas Developer products include iGen, a model framework generation system. iGen takes the laborious and error-prone task of constructing the various hardware model and software element files required for a typical model, and automates this process.

iGen takes as input a simple TCL specification that includes device internals such as registers and memories, port information,  component descriptors, and other elements.

iGen builds three sets of model items, C code model files, user editable templates, and XML descriptions. These include model frameworks with registers, function calls, memory map, and other items, including matching XML information. It ensures that all component parts of the model are well-structured using best practices, and are consistent throughout the files, thus eliminating a common source of errors.

Flow using iGen to generate platform and peripheral models

iGen presents to the developer a set of function calls and model elements that simply need to be filled in with required behavior, thereby reducing the set up overhead of a new model significantly. iGen also creates code in the model to provide very efficient run time tracing and diagnostics.





The OVP Open Source Modeling Infrastructure

Open Virtual Platforms (OVP) is an open industry initiative designed to provide a common infrastructure, models and interfaces for the development of highly efficient virtual platforms. Imperas donated to the initiative a set of APIs, open source models, and a reference simulation engine with the intent of enabling an easily to utilize, complete solution for companies wishing to create platforms for their internal or external embedded software teams. The OVP initiative is very  successful with many users of the technology from hobbyists, universities, commercial companies, and advanced research facilities.

One reason for the extensive range of processors and other models included in the Imperas library is ease of modeling provided by the OVP APIs. APIs are available for modeling platforms, processors, behavioral models / peripherals respectively, each optimized for the particular modeling style required. The modeling standards allow for functionality to be included quickly while maintaining model performance and ease of use, reducing a typical multi-month model development project down to just a few weeks.

Overview of OVP architecture

OVP models can be used in platforms written in C or in platforms written in SystemC TLM2.0.

The processor and peripheral models are delivered with a C bus transactional interface that is used in C based OVP platforms, and this interface is used to provide a high speed TLM 2.0 interface layer that allows the model to be used in a SystemC TLM 2.0 environment with the fastest possible simulation performance.

The Imperas Simulation System

At the core of all Imperas solutions is a fully functional simulation system that operates at the highest performance of any virtual platform simulator available today. The simulator is designed to allow embedded software to be executed on a modeled (virtual) platform for the purposes of verification, analysis, debug, profiling, fault injection, and regression testing. Its purpose within the Developer products is to execute the various models, to interface the models to the appropriate selected tools, to run software on the processor models, and to enable the tasks of OS and driver bring-up, or initial embedded software development.

The Imperas models and simulator enable high performance simulation of systems running embedded software using the production un-modified binaries of the embedded software. The embedded software running cannot tell that it is not running on physical hardware but is running on a simulated, virtual platform model, of the physical hardware.

Models of the processor and other components are created in C using the OVP APIs, as described in the OVP Infrastructure section. A full range of single, and homogeneous and heterogeneous multicore processors are supported through the simulation engine, based on the respective Developer product utilized. The simulator also supports any style of bus topology and can be used in C or C++/SystemC environments. All models in the Imperas model library can be in used in C or SystemC platforms, and the models are provided with native SystemC TLM2 interfaces.

The simulator utilizes Just-In-Time code morphing to enable particularly high-performance execution speed on standard x86 desktop computers, see the table below. By generating execution code on the fly, and combining this with other Imperas proprietary optimization schemes, the simulation performance that is achieved allows embedded code to be executed, often, faster than real time. Very large numbers of tests may be executed on embedded code within reasonable timescales, allowing product quality to be increased.

In addition, an extension of this mechanism, the Imperas ToolMorphing technology, allows for a highly streamlined integration of the Imperas software development kit, minimizing the traditional performance overhead and enabling tool usage without impact on software execution accuracy.

Speed Chart

Embedded Software Debugging

The simulator can operate with GNU’s GDB debugger, with or without the Eclipse IDE. The Imperas Multicore Software Development Kit (M*SDK) may be used which allows an extensive range of options for the verification, analysis and profiling of designs. The M*SDK also contains a powerful, three-dimensional debugger (temporal, spatial and abstract) that is CPU- and OS-aware and which adds to GDB-like functionality a series of options to target complex homogeneous/heterogeneous multicore platform debug.

C*DEV/S*DEV/M*DEV Feature Table

The three Developer packages are designed to target different processor configurations and use models. The table below illustrates the differences:

C*DEV/S*DEV/M*DEV Feature Table


See the model families available from OVPworld