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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

With the advent of RISC-V we have seen new design verification challenges emerge, and have been working with customers and open-source partners, as well as simulation vendors including Synopsys, since 2019 to develop RISC-V processor verification methodology. The outcome of this work is a co-simulation methodology where the device under test (DUT) and the reference model of the processor are run in lock-step, each executing the same program. The internal state of the two is continuously compared at the retirement of every instruction. Mismatches are reported immediately, enabling debug at the point of first failure. Another advantage to this methodology is that the reference model has the ability to respond to asynchronous events.  

To request the applications note, please email info@imperas.com.

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Comments

  • Hirohiko Ono, Senior Manager of the MCU Tools Marketing Department

    Renesas Electronics Corporation

    Imperas with its OVP Fast Processor Models is addressing key issues in software development for embedded systems. We are happy to work with Imperas to ensure that high quality models are easily available to our worldwide customers, helping them to develop and test software faster and more easily using virtual platforms.

  • Dr. Charlie Su, CTO and EVP

    Andes Technology

    All Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level.

    Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.