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Imperas presenting at IP-SoC Silicon Valley, April 24 2023

Imperas is participating at the Design & Reuse IP-SoC event with a presentation on the new verification ecosystem supporting the growth in RISC-V adoption by SoC developers.

 

IP SoC Silicon Valley 2023

 

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced their participation at the D&R IP-SoC Silicon Valley 2023, including a technical presentation, in-person demonstrations, and discussions on the latest methodologies for RISC-V verification.

 

Presentation: The Lost Art of Processor Verification
Abstract: 
The open standard ISA of RISC-V offers new design flexibilities and possibilities that is already impacting on the design side of many SoC projects. An optimized processor overs to unlock hidden value in performance, power savings, security, differentiated features, and an enduring market advantage.
But while every SoC design team now has a free architecture license to build a custom RISC-V processor or extend an existing core with custom instructions, this also represents a surge in verification work and a step-change in complexity.
This talk outlines the vision for the RISC-V verification ecosystem with resources available to all adopters based on new standards and methodologies, while leveraging established SoC verification methods with UVM and SystemVerilog. RISC-V represents a massive migration in verification responsibility and the creation of a new verification ecosystem.

Speaker:    Larry Lapides – Imperas Software
When:        April 24, 2023 – TBD PDT


For more information or to request meeting with the Imperas staff during IP SoC Silicon Valley 2023 please contact info@imperas.com.

 

About D&R IP-SoC Silicon Valley 2023
Design & Reuse IP-SoC Silicon Valley 2023 will be held at the Hyatt Regency Santa Clara, 5101 Great America Parkway, Santa Clara, CA, USA on April 24 2023. For registration and more information, click here.

 

 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

All trademarks or registered trademarks are the property of their respective holders.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

Using OVP Fast Processor Models with OVPsim and other simulators

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Philippe Berger, CEO

    Dolphin Design

    Our verification methodology for the Panther DSP/AI Accelerator IP needs to address not just the full range of the current configuration options but also the roadmap for Panther. 

    ImperasDV is the cornerstone of our simulation-based DV strategy, with the Imperas golden reference model, scoreboard, verification IP, functional coverage analysis and debug efficiency.

  • Chris Porthouse, Chief Product Officer

    Imagination Technologies

    The pace of innovation in markets such as the latest 5G communication networks and infrastructure offers many opportunities for new domain-specific SoC solutions.

    As a leading supplier of silicon IP, we fully appreciate the role of the ecosystem in supporting our lead customers in delivering new devices to market. We are pleased Imperas have now released the first Catapult RISC-V CPU Imperas reference model for the IMG RTXM-2200, which provides our mutual customers a proven path to accelerate projects to market.