Imperas is participating at the Design & Reuse IP-SoC event with a presentation on the new verification ecosystem supporting the growth in RISC-V adoption by SoC developers.
Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced their participation at the D&R IP-SoC Silicon Valley 2023, including a technical presentation, in-person demonstrations, and discussions on the latest methodologies for RISC-V verification.
Presentation: The Lost Art of Processor Verification
The open standard ISA of RISC-V offers new design flexibilities and possibilities that is already impacting on the design side of many SoC projects. An optimized processor overs to unlock hidden value in performance, power savings, security, differentiated features, and an enduring market advantage.
But while every SoC design team now has a free architecture license to build a custom RISC-V processor or extend an existing core with custom instructions, this also represents a surge in verification work and a step-change in complexity.
This talk outlines the vision for the RISC-V verification ecosystem with resources available to all adopters based on new standards and methodologies, while leveraging established SoC verification methods with UVM and SystemVerilog. RISC-V represents a massive migration in verification responsibility and the creation of a new verification ecosystem.
Speaker: Larry Lapides – Imperas Software
When: April 24, 2023 – TBD PDT
For more information or to request meeting with the Imperas staff during IP SoC Silicon Valley 2023 please contact email@example.com.
About D&R IP-SoC Silicon Valley 2023
Design & Reuse IP-SoC Silicon Valley 2023 will be held at the Hyatt Regency Santa Clara, 5101 Great America Parkway, Santa Clara, CA, USA on April 24 2023. For registration and more information, click here.
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