Imperas participating at the online virtual event highlighting the RV32/64K Crypto (scalar) Architectural Validation Test Suites for the RISC-V Verification Ecosystem.
Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced their participation at the RISC-V Forum on Security, April 14th 2021. An online virtual event covering the latest trends and developments on security, and how the RISC-V Ecosystem is developing the latest tools and solutions.
Imperas will present an introduction to the open source Architectural Validation tests for RISC-V Crypto “K”. The new scalar cryptography extension for RISC-V is designed to be lightweight and to be suitable for 32- & 64-bit base architectures, from embedded, IoT class cores to large, application class cores. The Architectural Validation Test Suites help RISC-V developers test the implementations are in-line with the specifications. This talk covers the use of the open source Crypto architectural validation test suites as part of a RISC-V processor test pan, including the key resources and setup guides.
Getting started with Architectural Validation tests for RISC-V Crypto “K”
Featured as part of the RISC-V International Security Overview
• Speaker: Simon Davidmann – Imperas Software
• When: April 14th 2021 7:05am PST
Free! Registration is free for the RISC-V Forum on Security, see more details this link.
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.
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