Imperas at DAC - Design Automation Conference, July 10-14 2022

Imperas will be participating at DAC 59 with presentations, panels, exhibits and in-person demos of ImperasDV for RISC-V Processor Functional Verification.

Imperas Software Ltd., the leader in simulation solutions for RISC-V, today announced their participation at DAC 2022 with presentations and exhibition booths #2336 and #2340 for demos and in-person discussions.

Panel: Those Darn Bugs! When Will They be Exterminated for Good?
The question many DAC attendees ask is whether bug eradication will ever become a reality. The panel will explore this topic in detail to find out what’s causing the industry to not scale verification to the point that we can sign off our chips on time, the first time with zero bugs. 
Who:          Ashish Darbari - Axiomise
                     Mark Glasser - Cerebras
                     Ty Garibay – Mythic AI
                     Simon Davidmann - Imperas
                     Brian Bailey (Moderator) - Semiconductor Engineering
When:        Monday July 11, 3:00pm-3:45pm PDT
Where:       DAC Pavilion (#2260)

Panel: RISC-V: Open and Flexible, but still a Standard?
This panel will explore ‘how well has RISC-V performed as an open standard ISA that encourages innovation without chaos and fragmentation?’
Who:           Himanshu Sanghavi (Organizer) - Meta
                     Pierre Selwan - Microchip
                     Yunsup Lee - SiFive
                     Charlie Cheng - Andes
                     Larry Lapides - Imperas
                     Jim Wang – Meta
                     Edward Sperling (Moderator) - Semiconductor Engineering
When:         Wednesday July 13, 1:30pm-3:00pm PDT
Where:        Engineering IP Track (Room # 2012, Level 2)

Talk: Introduction to RISC-V Verification with new open standard RVVI (RISC-V Verification Interface)
Abstract
As an open standard ISA, RISC-V has attracted the attention of system designs, hardware engineers and software developed based on the new freedoms for design optimizations. The OpenHW Group has been formed by members looking to build on the potential of open-source hardware IP as a foundation for further extensions and adoption in mainstream commercial designs. With this surge in design innovation the challenge for the verification task is not just the complexities on modem processor design innovations, but the scale of projects as the DV task moves from a few specialist providers to all adopters that chose to exploit the full potential now available with RISC-V for optimized processors in domain specific applications.
This talk will highlight the key aspect of a RISC-V verification plan based on the pioneering work at OpenHW to deliver quality open-source IP cores with industrial strength versification for adoption in the established commercial tools and design flows. With a case study around the CV32E40P as an example for the latest methods of ‘lock-step-compare’ for asynchronous events and debug operations. The new open standard of RVVI (RISC-V Verification Interface) supports the full flexibility of RISC-V for designs with privilege modes, vectors, out-of-order pipelines, multi-threading, multi-heart, plus user defined custom instructions and extensions. 
The design side flexibility of RISC-V is driving the innovation in functional verification, RVVI has the flexibility to support the efficiency and verification IP reuse as RISC-V becomes mainstream. 
Speaker:    Aimee Sutton – Imperas Software
When:        Monday July 11, 2:30pm-3:15pm PDT
Where:       Open-Source Central Theater #2338

Talk: RISC-V Models for Verification, Software Development and Architectural Exploration
Abstract
As RISC-V processors start to be used more and more in SoCs, industry needs to look beyond the RISC-V ISA to the requirements for use. These include a well-verified implementation, the ability to develop, debug and test software, especially early in the project, and the need to explore different implementations, including different processors, multi-hart processors and custom instructions.  One common element to these requirements is a high-quality model of the RISC-V cores being used.  This presentation will report on the test-driven development methodology used to build the Open Virtual Platforms (OVP) models of RISC-V cores (~100 different cores available in the OVP Library and provided to processor IP developers), and show how these models have been used for design verification, software development and architectural exploration. 
Specifically, this presentation will discuss how the availability of high-quality models of RISC-V processors impacts the design process, including in design verification (DV), software development and architecture exploration.  This talk will show examples of industry uses of these models for those use cases, including step-and-compare DV flows, software and operating system porting and bring up, and analysis and optimization of custom instructions.  
Speaker:    Larry Lapides – Imperas Software
When:        Tuesday July 12, 1:30pm-2:15pm PDT
Where:      Open-Source Central Theater #2338

Exhibit: While attending DAC please visit the Imperas booth #2336 and also on the OpenHW pavilion at booth #2340 to see all the latest demonstrations of ImperasDV for RISC-V processor verification, plus virtual platforms for software development. For more information, or to schedule a demonstration session at DAC 2022, please contact the Imperas team via info@imperas.com.
 

 
About DAC 2022
For more information see https://www.dac.com/
 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

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