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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

SemiEng: The Drive Toward Virtual Prototypes

Prototypes are transforming rapidly to take on myriad tasks, but they are hampered by a lack of abstractions, standards, and interfaces.

Semiconductor Engineering

 

Chipmakers are piling an increasing set of demands on virtual prototypes that go well beyond its original scope, forcing EDA companies to significantly rethink models, abstractions, interfaces, view orthogonality, and flows.
The virtual prototype has been around for at least 20 years, but its role has been limited. It has largely been used as an integration and analysis platform for models that are more abstract than implementation models. At its heart is an instruction set model for one or more processors, enabling early software development to be conducted on a fast, functionally accurate model of the hardware. Performance historically has relied on abstracting out timing information.
The term ‘shift left’ is being applied to an increase percentage of the tasks performed during system development. It provides an early glimpse of the impact that downstream decisions will have so that bad decisions can be caught earlier when their impact is limited…

 

To read the full Semiconductor Engineering article by Brian Bailey, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

Using OVP Fast Processor Models with OVPsim and other simulators

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Philippe Berger, CEO

    Dolphin Design

    Our verification methodology for the Panther DSP/AI Accelerator IP needs to address not just the full range of the current configuration options but also the roadmap for Panther. 

    ImperasDV is the cornerstone of our simulation-based DV strategy, with the Imperas golden reference model, scoreboard, verification IP, functional coverage analysis and debug efficiency.

  • Tony King-Smith, EVP Marketing

    Imagination Technologies

    We are delighted to be working with Imperas to deliver the fastest Instruction Accurate (IA) simulation solution for our many MIPS partners. We have been impressed how Imperas’ simulation technology significantly outperforms other commonly-used solutions. Faster simulation results in more tests being run, and therefore higher quality software being developed - and that is good news for our extensive MIPS ecosystem community.  Since acquiring MIPS, Imagination has committed to working more closely with innovative partners like Imperas to deliver superior CPU modelling solutions. As a result, we are confident our MIPS licensees and many software ecosystem partners will have access to the best tools in the industry, enabling them to create the best possible software and products.