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Imperas and Synopsys collaborate on SystemVerilog based RISC-V verification

Imperas Software, a specialist in RISC-V models and simulation solutions, is working with Synopsys to address the growing demand for RISC-V processor verification.

New Electronics

This collaboration [between Synopsys and Imperas] is intended to enable mutual customers to streamline their RISC-V verification tasks using ImperasDV verification solutions and Synopsys’ VCS simulation and Verdi debug tools for improved efficiency to achieve critical time-to-market and quality objectives.

ImperasDV is the first commercially available verification IP for RISC-V processors including architectural validation test suites that RISC-V developers need to ensure hardware implementations are in line with the expectations of the software ecosystem supporting RISC-V. It has native support for the open standard RISC‑V Verification Interface (RVVI) and uses a ‘lock-step-compare’ co-simulation methodology for comprehensive processor verification including asynchronous events and debug operations…


To read the full New Electronics article by Neil Tyler, click here.