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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

RISC-V International: Developing standards-based verification environments for extensible RISC-V processor cores

The open ISA of RISC-V means any SoC developer can now design a custom processor - moving the verification task from a few specialist suppliers to all SoC developers. This article looks at the industrial-grade verification and open methodology as used by the OpenHW verification working group.

RISC-V Processor Design Verification (DV)

One of the appealing things about open-source is that it invites modification to the underlying technology. In the case of the RISC-V instruction set architecture (ISA), this includes adding user-defined extensions to the processor core itself. Naturally, this level of extensibility has implications on the design flow, particularly if the core is going to be instantiated in silicon within an SoC or ASIC device…

To read the full article published by RISC-V International, click here.
 

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Comments

  • Nobuyuki Ueyama, President

    eSOL TRINITY Co., Ltd.

    RISC-V is enabling a new wave of design innovation, and successful projects depend on quality processor IP and dependable design platforms that offer architecture exploration and early software development.

    Having supported the NSITEXE team on the extensive internal RISC-V processor verification, as well as on the virtual platform development task for multiple projects, the support team at eSOL TRINITY is now able to assist developers as they build the next generation of SoC designs using the Imperas tools and reference models for the NSITEXE Akaria processors.

  • Dr. Charlie Su, President and CTO

    Andes Technology Corp.

    RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations.

    The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.