Imperas and Andes are co-hosting the next RISC-V Boston Group Meeting on optimizing a RISC-V processor with Vector Extensions for AI applications.
Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced the next Austin RISC-V group meeting which will be co-hosted with Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V CPU cores and a Founding Premier member of RISC-V International. The agenda will be focused around exploring and extending RISC-V Vector Accelerators for AI and other applications with talks by Andes, Imperas and guest speaker Dave Baker, VP Digital Design at Luminous Computing who will share Comments on Experiences with RISC-V ISA.
Memory Bandwidth: The Real Challenge for RISC-V Vector Processors
John Min, Andes Technology
Combining large numbers of RISC-V Vector processors to solve a common machine learning problem such as image recognition is a function vector processor are well suited for. In this meetup, presenters will describe how the power of the RISC-V Vector processor tackles this problem. They will also offer a solution to the memory bandwidth bottleneck common in large multiprocessor arrays.
Software development: The Critical Path for AI SoC
Katherine (Kat) Hsu, Imperas Software
An inference SoC for AI/ML – data center or edge – typically has an application processor plus AI accelerator. The AI accelerator will likely be an array of processors and vector engines. This requires optimization of the AI software plus the software managing the workload balancing. This talk will discuss the different tasks of software development for AI SoCs, and how a virtual platform enables the “shift left” of schedules, many months before a FPGA prototype or hardware emulator is available.
When: Tuesday October 5th 2021 at 6:00pm EDT
Where: Virtual Event
Free registration and more details are available at this Link.
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