x

Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

SemiEng: How To Optimize A Processor

There are at least three architectural layers to processor design, each of which plays a significant role.

Semiconductor Engineering

 

Optimizing any system is a multi-layered problem, but when it involves a processor there are at least three levels to consider. Architects must be capable of thinking across these boundaries because the role of each of the layers must be both understood and balanced.
The first level of potential optimization is at the system level. For example, how does data come in and out of the processing cores? The next level is the architecture of the processing cores themselves. This may involve adopting an existing processor, or adding instructions to an extensible core. The final level of optimization is the micro-architectural level. This is where implementation pipelines are defined…

 

To read the full Semiconductor Engineering article by Brian Bailey, click here.


##

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Comments

  • Mike Bartley. Founder & CEO

    Test and Verification Solutions Ltd.

    With software now a key deliverable in semiconductor products, our customers increasingly need to develop hardware and software in parallel to hit ever-decreasing market windows, and virtual platforms are a key technique in achieving that. Our partnership with Imperas thus allows T&VS to enhance the solutions we can offer to the market. I am particularly excited by the Imperas fault injection capability which is a key verification technique in the growing safety markets such as automotive.

  • Joon Pang, CEO

    Coontec Korea

    Coontec has seen that Imperas offers the best portfolio of virtual prototyping and simulation solutions in the world. Our partnership allows us to offer customers a comprehensive solution to enable shorter time-to-market and enhanced reliability in software development, debug, and test. Imperas will bring greater security and speed to our customers' development projects than ever before.