Imperas Software announced the latest updates to ImperasDV to support the rapid growth in RISC-V verification as developers extend into established and emerging applications with new design innovations based on the flexibility of RISC-V. ImperasDV is the integrated solution for RISC-V processor verification that supports both RTL bug detection and analysis, when combined with design flow integration for the leading EDA SystemVerilog environments with Cadence, Siemens EDA, and Synopsys.
Design Verification (DV) teams use coverage analysis as the key metric for progress toward the completion of verification plans. For the open standard specification of RISC-V, a coverage library can be configured based just on the specification definition. However, since a processor has many complex states due to privilege modes, interrupts and dynamic effects, the coverage library needs to consider the complete operational behaviour of a processor, not just a block-level functional unit….
To read the full Electronic Specifier article by Beth Floyd, click here.