The DVCon 2021 edition of Siemens EDA Verification Horizons.
The open standard ISA of RISC-V allows SoC developers to also build or modify a processor core optimized to the application requirements. The SoC verification tasks are adapting to address the significant increases in complexity. This article covers the 6 key components of RISC-V processor verification: The DV Plan, RTL DUT, Testbench, Tests, Reference model, and Siemens EDA Questa SystemVerilog simulation environment.
Within the RISC-V specification many standard extensions and options are available in addition to any user defined custom instructions. While some processor DV aspects may appear similar to a modern SoC verification flow, the flexibility of the open standard ISA of RISC-V makes almost every step uniquely challenging. This article provides some insights with the development of the latest architectural validation test suites for the RISC V Vectors draft specification, using Siemens EDA Questa with a UVM SystemVerilog testbench, including coverage analysis and results…
To read the full Verification Horizons article, click here.