Zbyszek Zalewski, General Manager, Hardware Division
The integration of HES with OVPsim enables hardware and software design teams to implement virtual models of processors, memory and peripherals while the RTL modules run in the emulator board. This new integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.
Hugh O’Keeffe, CEO
We are excited to offer our customers target debug support for the Imperas golden reference models of the MIPS eVocore P8700 Multiprocessor.
This collaboration between Ashling, MIPS, and Imperas enables developers to accelerate their RISC-V software development, testing, and debugging, ultimately leading to faster time-to-market for next-generation domain-specific devices.