Imperas Announces Ratifications, Test Suites, and Functional Coverage Libraries for RISC-V

Imperas Software Ltd. revised its ImperasDV for maintaining the expansion of RISC-V verification supporting both RTL bug detection and analysis while collaborating with design flow implementation in EDA SystemVerilog environments with Cadence, Siemens EDA, and Synopsys. Imperas leverages RISC-V for its ability to be customized for specific industry needs. “RISC-V offers new freedoms in design flexibility which is driving a new wave of innovation across the semiconductor industry in almost all market segments,” said Larry Lapides, VP of Sales at Imperas 
Design Verification (DV) teams utilize coverage analysis as the key metric toward finalizing verification plans. The ImperasDV Verification IP extends to contain riscvISACOV, a collection of SystemVerilog source functional coverage libraries. For detailed information, visit https://github.com/riscv-verification/riscvISACOV ….
 

To read the full Embedded Computing Design article by Chad Cox, click here.

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