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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Imperas CEO Simon Davidmann Speaks at DATE 2016 in Germany

DATE 2016 Tutorial: Virtual Platforms in the Internet of Things (IoT) Era

OXFORD, United Kingdom, February 16, 2016 -- Imperas Software Ltd., leader in high-performance software simulation and virtual prototyping, today announced that CEO Simon Davidmann will give a tutorial at DATE (Design, Automation & Test in Europe) 2016. DATE is a leading international event for design and engineering of systems-on-chip, systems-on-board and embedded systems software. Imperas CEO Simon Davidmann will provide an introduction to virtual platforms, speaking on embedded software development, debugging, analysis, and verification with virtual platforms supporting today's multiprocessor SoCs, as part of the tutorial “Internet-of-Things: Virtual Platforms in the Internet-of-Things Era – State of the art and perspectives.” 

Smart embedded systems are the building blocks of the Internet-of-Things (IoT). In embedded system design, it is well known that the software development effort has overtaken the hardware effort. Virtual platforms can address this mismatch by enabling parallel software and hardware development. Verification and testing of software for IoT and smart embedded systems, including operating systems, drivers, firmware and applications, require a continuous evolution of virtual platform methodologies.

Ever more powerful multiprocessor SoCs allow exploiting concurrency, while executing multiple applications on the same chip can impact extra-functional properties (e.g., time, power and temperature); these must be analyzed. New operating systems and hypervisors, for improved control, security and safety of the system, must be ported and tested. Smart systems are ever more connected, with continuous-time behavior to be simulated together with discrete-time models, and legacy RTL components with virtual platforms. Interaction among systems must be verified in realistic network scenarios.

This tutorial will give insights into which changes to expect in new virtual platforms regarding efficient CPU simulation, analog-mixed-signal modeling, simulation of extra-functional properties and network simulation, and how these changes can help to design tomorrow’s embedded systems more efficiently.

Where: The International Congress Center (ICC) in Dresden, Germany.

When: DATE is March 14–18, 2016. The tutorial is March 14, 2016, 14:30-18:00 PM.

Please contact sales@imperas.com to learn more about Imperas virtual prototyping solutions for embedded software development, debug and test; or to set up a meeting at DATE 2016.

For more information on DATE, see www.date-conference.com.

About Imperas

For more information about Imperas, please see www.imperas.com.

All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

ARM TrustZone Platform Modeling Application Note

RISC-V Custom Instruction Flow Application Note

Comments

  • Nobuyuki Ueyama, President

    eSOL TRINITY

    Virtual platforms enable the essential early development of software well before RTL or silicon prototypes are available, which dramatically accelerates the time to market.

    In addition, for the next generation of automotive AI designs, the early architectural exploration of the SoC helps validate the system design and becomes the reference model for RTL verification.

  • Nobuyuki Ueyama, President

    eSOL TRINITY Co., Ltd.

    RISC-V is enabling a new wave of design innovation, and successful projects depend on quality processor IP and dependable design platforms that offer architecture exploration and early software development.

    Having supported the NSITEXE team on the extensive internal RISC-V processor verification, as well as on the virtual platform development task for multiple projects, the support team at eSOL TRINITY is now able to assist developers as they build the next generation of SoC designs using the Imperas tools and reference models for the NSITEXE Akaria processors.