Imperas with Andes and UltraSoC co-hosting a webinar on the latest challenges’ designers are facing migrating AI/ML applications to custom SoCs with RISC-V
Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their participation together with Andes and UltraSoC with a webinar for SoC designers developing next generation devices to learn how to better optimize, test, and evaluate multicore RISC-V designs for AI inferencing and machine learning applications.
Webinar: “Multicore RISC-V Designs in AI & Machine Learning Applications”
Outline: This webinar will cover the latest challenges’ designers are facing when accelerating AI/ML application with custom SoCs and RISC-V.
Artificial Intelligence (AI) and Machine Learning (ML) are among the fastest growing market segments as designers look to optimize domain specific SoC devices to accelerate complex algorithms and applications. While highlighting the latest examples for these applications many of the techniques and insights can also be applied to any RISC-V based SoC design.
This webinar will cover the key SoC design stages of:
• Architectural exploration: Software driven prototype analysis with virtual platforms
• RISC-V core configuration: Optimized features for cores and processor sub-systems
• Full on-chip instrumentation: Debug and trace, plus on-chip performance monitors
Held on Wednesday May 6th 2020 – Recording Now Available!
With two meeting time slots available to choose from:
Meeting at 8am (PDT) or 5pm (PDT)
City time zone comparisons:
San Jose: 8am (PDT) or 5pm (PDT)
London: 4pm (BST) or 1am (BST on May 7th)
Paris: 5pm (CET) or 2am (CET on May 7th)
Bangalore: 8:30pm (IST) or 5:30am (IST on May 7th)
Taipei: 11pm (CST) or 8am (CST on May 7th)
Webinar replay now available on demand at this link.
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.
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