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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

SemiEng: Choosing Which Tasks To Optimize In Chips

Most applications can be decomposed into a number of tasks, and there are many options to create better implementations of them.

Semiconductor Engineering

 

The optimization of one or more tasks is an important aspect of every SoC created, but with so many options now on the table it is often unclear which is best.
Just a few years ago, most people were happy to buy processors from the likes of Intel, AMD and Nvidia, and IP cores from Arm. Some even wanted the extensibility that came from IP cores like Tensilica and ARC. Then, in 2018, John Hennessy and David Patterson delivered the Turing Lecture titled “A New Golden Age for Computer Architecture: Domain-Specific Hardware/Software Co-Design, Enhanced Security, Open Instruction Sets, and Agile Chip Development.” While it was not the lecture that started the drive towards more optimization, it certainly elevated it to the global consciousness…

 

To read the full Semiconductor Engineering article by Brian Bailey, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

RISC-V Custom Instruction Flow Application Note

Comments

  • Rick O’Connor, President & CEO

    OpenHW Group

    The OpenHW Verification Task Group contributors are pioneers in the drive to advance the quality of open-source hardware IP ready for mainstream adoption – quality deliverables are the hallmark of any trusted IP provider, commercial or open source.

    OpenHW membership growth over the past three years is expanding the roadmap of IP core projects dramatically, with projects addressing the needs for application class devices supporting Linux, embedded security, and compute intensive applications with custom instructions. The RVVI open standard and flexible methodology significantly helps the OpenHW Verification Task Group members and contributors with efficient and quality verification for the full range of CORE-V IP projects.

  • Itai Yarom, VP of Sales and Marketing

    MIPS, Inc.

    RISC-V is at the forefront of a hardware design renaissance in optimized processors.

    But, an ISA only provides the envelope of possibilities. The art and science of processor optimization requires complete feature exploration and verification, which are supported by the reference model simulation and verification technology from Imperas.