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SemiEng: The Challenges Of Incremental Verification

Is it possible to make a design change and not have to rerun the entire regression suite?

Semiconductor Engineering


Verification consumes more time and resources than design, and yet little headway is being made to optimize it. The reasons are complex, and there are more questions than there are answers. For example, what is the minimum verification required to gain confidence in a design change? How can you minimize the cost of finding out that the change was bad, or that it had unintended consequences?
In the design flow, tools and methodologies have been created to minimize the chance of problems, particularly as you approach tape-out, by making safe, non-optimal corrections. But there are no such tools or methodologies for verification. “You have tons of resources focused on verification,” says Simon Davidmann, founder and CEO for Imperas Software. “The goal is to minimize what design changes you make because with the technologies that are available today, when you change something in the design, you need to rerun everything…


To read the full Semiconductor Engineering article by Brian Bailey, click here.