Imperas Demonstrates Andes-Based RISC-V Virtual Platforms for Software Development and Testing
Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced they will co-host a RISC-V seminar in Korea with Coontec, Andes and UltraSoC on the Methodology for Designing a RISC-V SoC.
This seminar will provide engineers with an overview of the steps needed to build a RISC-V based SoC, including processor design (custom instructions) and verification, processor and SoC debug, and software porting and bring up. Examples of use cases will also be presented. Featured presenters will include Andes, Coontec, ETRI, Imperas, UltraSoC and other invited guests, plus demonstration and networking session to follow.
For more information, or to set up meetings with Imperas, please email firstname.lastname@example.org
Seminar: Methodology for Designing a RISC-V SoC
When: Thursday, May 30, 2019, 12:30pm – 6pm
Where: (13449) 232, LH Business Growth Center, 54, Changeop-ro, Sujeong-gu, Seongnam-si, Gyeonggi-do, Republic of Korea
Please visit this page to register.
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