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RISC-V Targets Data Centers

Open-source architecture is gaining some traction in more complex designs as ecosystem matures.

Semiconductor Engineering


RISC-V vendors are beginning to aim much higher in the compute hierarchy, targeting data centers and supercomputers rather than just simple embedded applications on the edge.
In the past, this would have been nearly impossible for a new instruction set architecture. But a growing focus on heterogeneous chip integration, combined with the reduced benefits of scaling and increasing demand for specialized accelerators, has opened the door wide to newcomers. There are an estimated 200 startups working on accelerators for AI/ML, and some of them are using RISC-V as a starting point.
What makes RISC-V particularly attractive is the ability to modify the source code. That has driven up its popularity in edge and embedded applications, but it also has sparked the interest of companies looking to use this open-source ISA for much higher-performance applications.

“In the beginning, it was very much targeted at low-end microcontrollers for cost-saving reasons,” said Simon Davidmann, CEO of Imperas Software. “Then it became people trying to do huge arrays of processes and high-end vectors. But in the last six months, there has been a lot of interest from companies pushing the envelope of high-capability cores, a mid-step between high-performance computing and embedded. These are cores that are multi-threaded, multi-core, multi-clustered, like a high-end Arm, and they’re pushing the speed envelope. They’re trying to go to 3 or 4 gigahertz, so these aren’t low-cost embedded cores, and they’re not huge arrays. They’re really high-performance application type of processors. What’s been seen in the RISC-V ecosystem initially was the low-end, ‘free’ efforts, to the high end ‘freedom’ work, now to these high performance cores, which shows that RISC-V as an architecture is applicable across all these different domains.”….

To read the full Semiconductor Engineering article by Ann Steffora Mutschler, click here.