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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

eeNews Europe: Open Standard RISC-V Verification Interface (RVVI)

eeNews Europe

Imperas Software in the UK has extended the RVVI (RISC-V Verification Interface) with virtual peripherals to support asynchronous events and system level interrupts. RVVI is an open specification with a common methodology for the key components of the testbench to connect the RISC-V processor RTL instruction trace and reference models to fully support the lock-step-compare co-simulation.

The RVVI flexibility supports the full range of RISC-V specifications and features that can be adopted with increasing levels of complexity for designs with privilege modes, vector extensions, out-of-order pipelines, multi-threading, multi-hart, plus user-defined custom instructions and extensions. RVVI supports the innovation of RISC-V with the flexibility required for verification IP and reuse as DV teams scale up to support the rapid growth in RISC-V verification projects…

 

To read the full eeNews Europe article by Nick Flaherty, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Custom Instruction Flow Application Note

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Dr. Luciano Ost

    Embedded Systems and Communications Research Group, University of Leicester

    The lack of electronic design automation (EDA) tools combining model flexibility, and fast and accurate evaluation of performance, power, and reliability is one of the major challenges currently faced by embedded researchers. Even expensive, commercially available tools don't often meet modeling and simulation needs for emerging technologies.The description of processors – i.e., register or gate-level – is rarely available to universities, and commercial licenses are quite expensive. Having free tools with different state-of-the-art processor models allows the exploration of new system architectures.

  • Itai Yarom, VP of Sales and Marketing

    MIPS, Inc.

    The eVocore P8700 Multiprocessor is our first RISC-V based IP core.

    As an open standard ISA, RISC-V provides a foundation for a basic level of compatibility across technologies in the ecosystem. Together with Imperas and Ashling we are going beyond that, enabling SoC designers and software developers to take advantage of the P8700’s advanced microarchitectural features using best-in-class models and tools.