Doing what has been done in the past only gets you so far, but RISC-V is causing some aspects of verification to be fundamentally rethought.
Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, senior director of alliances partner marketing at Synopsys; Dave Kelf, CEO of Breker Verification, and Hieu Tran, president and CTO of Viosoft Corporation. What follows are excerpts of that conversation.
SE: Arm and Intel seem to be the benchmarks, but neither ever had to deal with the customizability and extensibility that RISC-V has. Is following Arm and Intel the right path?
Hardee: I firmly believe RISC-V is going to be a huge player in domain-specific processing. Architecture licensees of Arm are able to configure the processor for specific domains. What we’re seeing with RISC-V is domain-specific data path processing being added to the RISC-V core to cover the various domains where it can find application. This is great. It is really powerful that RISC-V is able to do this. But, of course, it adds to the verification challenge.…
To read the full Semiconductor Engineering article by Brian Bailey, click here.