Does RISC-V processor verification provide common ground to develop a new verification methodology, and will that naturally lead to new and potentially open tools?
SE: Open source enables collaboration. Until now, no two companies have used the same verification methodology. RISC-V may be the first time that enough people have been working on a common problem to be able to devise a solution within the verification space.
Simon Davidmann, Imperas: If we focus on RISC-V. The challenge is that for the past 50 years, processors were built very secretly. You never shared how you designed it or how you verified it. Suddenly, here we are in the last five years, as everyone gets on the RISC-V bandwagon, everybody has become a computer architect, everybody’s got an architecture license, but they don’t have the verification methodology or understanding. There are proprietary solutions hidden away in the big processor vendors. We are building methodologies. We’re trying to work with people on standard interfaces so that reference models can be used in a standard way with test benches. There is a dramatic change that’s come about because of the open nature of RISC-V. It’s not just about building the tools and the methodologies. It’s supporting, maintaining, and developing it. What the EDA industry has achieved over the past 30 years is absolutely phenomenal. I don’t buy that open source is the solution for verification. What we need is better verification. We need to move forward, and it’s great that people are looking at things like Python and other solutions. AI is going to help us a lot in verification. We just don’t know it yet. And there’s a lot to be done. It’s not the cost of the software. The cost is in your people, in your brains, and doing smart things with it…
To read the full Semiconductor Engineering article by Brian Bailey, click here.