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Ventana Micro selects Imperas Solutions for RISC-V processor verification

Imperas have announced that Ventana Micro has selected Imperas simulation and test and verification solutions for the RISC-V processors under development as IP cores and chiplets.

Electronic Specifier

Ventana delivers RISC-V CPUs with domain specific workload acceleration capability delivered in the form of multi-core chiplets or core IP for applications in the data centre, automotive, 5G infrastructure, AI, and client markets. Ventana was founded by processor industry veterans, and is a member of the RISC-V International Board of Directors and its Technical Steering Committee.
Imperas provides a flexible framework for RISC-V processor verification that enables design verification teams to fully verify a processor implementation and accelerate time to market. Based on the trusted Imperas RISC-V reference models, verification IP, and Imperas architectural validation tests, Imperas also offers the dynamic comparisons of the processor implementation against the Imperas RISC-V reference model in a 'lock-step-compare' methodology which provides both accurate detection of issues, and the efficient resolution of bugs….
 

To read the full Electronic Specifier article by Kristian McCann, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

RISC-V Custom Instruction Flow Application Note

ARM TrustZone Platform Modeling Application Note

Comments

  • Krishna Raghavan, President

    MIPS IP Licensing, Wave Computing

    The Imperas simulation and modeling technology has been a reliable and high-quality testing model used internally by the MIPS engineering team for many years. We are delighted to partner with Imperas to make this industrial-grade simulation technology available to support the MIPS Open program and further the momentum around open hardware development.

  • Dr. Luciano Ost

    Embedded Systems and Communications Research Group, University of Leicester

    The lack of electronic design automation (EDA) tools combining model flexibility, and fast and accurate evaluation of performance, power, and reliability is one of the major challenges currently faced by embedded researchers. Even expensive, commercially available tools don't often meet modeling and simulation needs for emerging technologies.The description of processors – i.e., register or gate-level – is rarely available to universities, and commercial licenses are quite expensive. Having free tools with different state-of-the-art processor models allows the exploration of new system architectures.