Imperas is now a part of Synopsys
RISC-V, the open-source Instruction Set Architecture (ISA) that was thought to have no real chance of becoming a standard in the semiconductor market, now has 14% of the global processor market. This astounding accomplishment is due to the exceptional teams RISC-V employs. We look back over the company’s outstanding year and its advancements in the industry as well as those of its sister organizations, especially SiFive. Its journey is one bordered with skepticism but paved with remarkable success…
To read the full Circuit Cellar article by Stephen Vicinanza, click here.
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There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.
On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.
Publicly available Imperas documents:
Comments
Rick O’Connor, President & CEO
OpenHW GroupThe defining goal of the OpenHW group is to deliver high quality open source IP cores, by leveraging the leading verification methodologies compatible with the established EDA commercial SoC design flows.
To support our world class IP portfolio, the OpenHW working groups are enabling adoption with tools and software support for CORE-V processors. The Imperas contribution with the new free ISS, riscvOVPsimCOREV will be the foundation reference to all software tasks.
Charlie Hong-Men Su, CTO and Senior VP
Andes TechnologyThe Imperas virtual platform solutions for software development, debug and test, along with their open-source models, comprise an excellent methodology for development of embedded software for SoCs based on V5 AndesCore N25 and NX25 RISC-V processors.