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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV

The design freedoms of RISC-V offer developers flexibility for innovation – now processor IP verification quality is also a flexible option.

The Lost Art of Processor Verification

 

The RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address their target end application needs and requirements. RISC-V has a modular structure with many standard instruction extensions for additional dedicated hardware features such as Floating Point, Bit Manipulation, DSP, Cryptographic, Vectors, and many others currently under development. In addition, custom instructions can be added to further optimize the design. As RISC-V is an open standard specification, many implementations have been developed as commercial projects whilst others are made available as open-source hardware IP. Thus, SoC developers have several options in selecting a processor core, from developing a new design, selecting from the available cores, to modifying and enhancing any of these starting points…

To read the full blog post by Lee Moore and Simon Davidmann (Imperas Software) on Semiconductor Engineering, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

RISC-V Custom Instruction Flow Application Note

Comments

  • Shubhodeep Roy Choudhury, Managing Director & Co-founder

    Valtrix Systems

    Ideally any test should provide a clear pass or fail indication. In the case of RISC-V processor DV this is achieved with a comparison against a quality reference model.

    STING helps generate portable, architecturally correct and self-checking tests targeted at the corner-case scenarios by automating the comparison of the DUT against the Imperas reference model results.

  • Giddy Intrater, Vice President of Marketing

    MIPS Technologies

    Our new Aptiv Generation of cores pushes the boundaries in performance and efficiency. Having MIPS-Verified support from Imperas and OVP, a leading supplier of high-quality, fast processor core models, enables our customers to get started immediately with designs based on the Aptiv Generation cores.