Skip to main content

RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV

The design freedoms of RISC-V offer developers flexibility for innovation – now processor IP verification quality is also a flexible option.

The Lost Art of Processor Verification


The RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address their target end application needs and requirements. RISC-V has a modular structure with many standard instruction extensions for additional dedicated hardware features such as Floating Point, Bit Manipulation, DSP, Cryptographic, Vectors, and many others currently under development. In addition, custom instructions can be added to further optimize the design. As RISC-V is an open standard specification, many implementations have been developed as commercial projects whilst others are made available as open-source hardware IP. Thus, SoC developers have several options in selecting a processor core, from developing a new design, selecting from the available cores, to modifying and enhancing any of these starting points…

To read the full blog post by Lee Moore and Simon Davidmann (Imperas Software) on Semiconductor Engineering, click here.