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Imperas in the News

These latest models support the NS family of standard processors in safety critical and next-generation embedded systems, for developers using Imperas and other leading EDA tools

NSITEXE Qualifies Imperas RISC-V Reference Models for Aquaria Processors

Oxford, United Kingdom – December 13th, 2022 – Imperas Software Ltd.,the leader in RISC-V simulation solutions, today announced that NSITEXE, Inc., a group company of the DENSO Corporation that develops processor IP for functional safety and…

Electronic Specifier

 

 

Imperas Software announced the latest updates to ImperasDV to support the rapid growth in RISC-V verification as developers extend into established and emerging applications with new design innovations based on the flexibility of RISC-V. ImperasDV is the integrated solution for RISC-V processor verification that supports both RTL bug detection and analysis, when combined with design flow integration for the leading EDA…

ImperasDV is based on the trusted Imperas reference models and Verification IP, combined with architectural validation test suites and coverage libraries, and with native RVVI support

ImperasDV for RISC-V Verification

Oxford, United Kingdom – December 12th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates to ImperasDV to support the rapid growth in RISC-V verification as developers extend into…

Imperas reference model for IMG RTXM-2200 is available on request to lead customers for real-time embedded applications in next generation domain-specific SoCs

Imperas RISC-V Reference Model for Imagination Catapult

Oxford, United Kingdom – December 8th, 2022 – Imperas Software Ltd.,the leader in RISC-V simulation solutions, today announced that Imagination Technologies, a global technology leader in silicon IP (…

Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models, Verification IP, and test suites

MIPS selects Imperas for advanced RISC-V verification

Oxford, United Kingdom – December 7th, 2022 – Imperas Software Ltd.,the leader in RISC-V simulation solutions, announced today that MIPS, a leading developer of highly scalable RISC processor IP, has selected Imperas to provide advanced RISC-V…

Imperas leadership in the RISC-V Verification Ecosystem recognized in the expanded OpenHW Verification Task Group charter to lead the RISC-V community in adapting to the challenges of RISC-V processor verification

Simon Davidmann elected as Chair of the OpenHW Verification Task Group

Oxford, United Kingdom – December 5th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Simon Davidmann has been elected as Chair of the OpenHW…

Electronics Weekly

 

RISC-V intellectual property company Andes Technology has certified simulation reference models from Imperas reference for use evaluating multi-core designs featuring the functional-safety-optimised Andes Core N25F-SE. At the same time, it also certified the complete range of Andes processor IP blocks with ‘Andes Custom Extension’ (ACE) support. Such virtual references run exactly the same binary code as any…

Imperas reference models for Andes expanded with Andes Custom Extension™ support and design flow integration for leading EDA environments, plus new AndesCore® N25F-SE core for functional safety applications

Imperas and Andes for RISC-V Innovation

Oxford, United Kingdom – November 29th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V processor cores and…

Realizing the benefits of digital twins is more complicated than translating data between tools.

Semiconductor Engineering

 

Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale.
The glue between these various processes is data…