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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Simulation model certified for functional safety RISC-V core

Electronics Weekly

 

RISC-V intellectual property company Andes Technology has certified simulation reference models from Imperas reference for use evaluating multi-core designs featuring the functional-safety-optimised Andes Core N25F-SE. At the same time, it also certified the complete range of Andes processor IP blocks with ‘Andes Custom Extension’ (ACE) support. Such virtual references run exactly the same binary code as any resulting hardware would. “Functional safety applications demand a high standard of system and software quality which in turn has implications for the project planning, tools and methodology,” according to Imperas. “Functional safety is not just about resolving traditional software bugs and errors but also subjecting the entire platform to exceptional situations and functional stress conditions.”….
 

To read the full Electronics Weekly article by Steve Bush, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Custom Instruction Flow Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Itai Yarom, VP of Sales and Marketing

    MIPS, Inc.

    The eVocore P8700 Multiprocessor is our first RISC-V based IP core.

    As an open standard ISA, RISC-V provides a foundation for a basic level of compatibility across technologies in the ecosystem. Together with Imperas and Ashling we are going beyond that, enabling SoC designers and software developers to take advantage of the P8700’s advanced microarchitectural features using best-in-class models and tools.

  • Rick O’Connor, President & CEO

    OpenHW Group

    One aspect that all RISC-V processor designers agreed on, both commercial vendors and open-source developers, is that quality is the key to successful IP core adoption.

    The OpenHW Group have supported the adoption of RVVI from its inception through the member contributors in the OpenHW Verification Task Group, and now welcome the new features and growing adoption by the commercial community.