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Imperas and Industry Articles

The DVCon 2021 edition of Siemens EDA Verification Horizons.

Verification Horizons

 

The open standard ISA of RISC-V allows SoC developers to also build or modify a processor core optimized to the application requirements. The SoC verification tasks are adapting to address the significant increases in complexity. This article covers the 6 key components of RISC-V processor verification: The DV Plan, RTL DUT, Testbench,…

The actual time may be more of a fuzzy risk assessment than a clear demarcation.

Semiconductor Engineering

 

Even with the billions of dollars spent on R&D for EDA tools, and tens of billions more on verification labor, only 30% to 50% of ASIC designs are first time right, according to Wilson Research Group and Siemens EDA.
Even then, these designs still have bugs. They’re just not catastrophic enough to cause a re-spin. This means more efficient verification is needed. Until then, verification teams continue to…

OpenHW Processor DV Flow with Imperas RISC-V Golden Reference Model

 

The RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition, implementations may be shared commercially or as open-source, and adopters beyond the original design team can use these directly or as a basis for further modifications and enhancements.
The OpenHW Group is a not-for-…

High-quality and efficient verification requires a focus on details.

Semiconductor Engineering

 

Verification is undergoing fundamental change as chips become increasingly complex, heterogeneous, and integrated into larger systems.

Tools, methodologies, and the mindset of verification engineers themselves are all shifting to adapt to these new designs, although with so many moving pieces this isn’t always so easy to comprehend. Ferreting out bugs in a design now requires a multi-faceted and more holistic approach,…

Using SoC methodologies for RISC-V processor DV.

The Lost Art of Processor Verification

 

As we celebrate over 50 years of microprocessors, the industry has embraced every generation of silicon process technology with architectural innovation plus new design methods that have supported innovations in almost every market segment. The interest around RISC-V is opening up increased activity around new approaches to optimize designs for the next generation of devices across multiple market segments…

 

To…

The semiconductor industry will look and behave differently this year, and not just because of the pandemic.

Semiconductor Engineering

 

The new year will be one of significant transition and innovation for the chip industry, but there are so many new applications and market segments that broad generalizations are becoming less meaningful. Unlike in years past, where sales of computers or smart phones were a good indication of how the chip industry would fare, end markets have both multiplied and splintered, greatly increasing the number…

Complexity is making this process more difficult, but new and better approaches are being developed.

Semiconductor Engineering

 

The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches.
Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact…

The role of engineers is changing, and they need to be picking up new skills if they are to remain valuable team players. There are several directions they could go in.

Semiconductor Engineering

 

Engineering has one constant — you innovate or fall by the wayside. That is true both for the things that are designed and for the engineers who design and build them. Today’s systems are putting new strains on engineers who can no longer be “tall and thin” or “short and fat.” Those descriptions pertain to an engineer who is either highly…

Continuous design innovation adds to verification complexity, and pushes more companies to actually do it.

Semiconductor Engineering

 

The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies.

The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature,…